[media] ddbridge: Initial check-in
Driver support for Digital Devices ddbridge-based cards: Octopus, Octopus mini, Octopus LE, cineS2(v6) with DuoFlex S2 and/or DuoFlex CT tuners. Driver was taken from ddbridge-0.6.1.tar.bz2. Signed-off-by: Ralph Metzler <rmetzler@digitaldevices.de> Signed-off-by: Oliver Endriss <o.endriss@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Ralph Metzler
Mauro Carvalho Chehab
parent
af070bd60f
commit
ccad04578f
1690
drivers/media/dvb/ddbridge/ddbridge-core.c
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1690
drivers/media/dvb/ddbridge/ddbridge-core.c
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File diff suppressed because it is too large
Load diff
151
drivers/media/dvb/ddbridge/ddbridge-regs.h
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151
drivers/media/dvb/ddbridge/ddbridge-regs.h
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/*
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* ddbridge-regs.h: Digital Devices PCIe bridge driver
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*
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* Copyright (C) 2010-2011 Digital Devices GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 only, as published by the Free Software Foundation.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA
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* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
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*/
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// $Id: DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred $
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// Register Definitions
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#define CUR_REGISTERMAP_VERSION 0x10000
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#define HARDWARE_VERSION 0x00
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#define REGISTERMAP_VERSION 0x04
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// --------------------------------------------------------------------------
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// SPI Controller
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#define SPI_CONTROL 0x10
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#define SPI_DATA 0x14
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// --------------------------------------------------------------------------
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// Interrupt controller
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// How many MSI's are available depends on HW (Min 2 max 8)
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// How many are usable also depends on Host platform
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#define INTERRUPT_BASE (0x40)
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#define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00)
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#define MSI0_ENABLE (INTERRUPT_BASE + 0x00)
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#define MSI1_ENABLE (INTERRUPT_BASE + 0x04)
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#define MSI2_ENABLE (INTERRUPT_BASE + 0x08)
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#define MSI3_ENABLE (INTERRUPT_BASE + 0x0C)
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#define MSI4_ENABLE (INTERRUPT_BASE + 0x10)
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#define MSI5_ENABLE (INTERRUPT_BASE + 0x14)
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#define MSI6_ENABLE (INTERRUPT_BASE + 0x18)
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#define MSI7_ENABLE (INTERRUPT_BASE + 0x1C)
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#define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20)
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#define INTERRUPT_ACK (INTERRUPT_BASE + 0x20)
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#define INTMASK_I2C1 (0x00000001)
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#define INTMASK_I2C2 (0x00000002)
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#define INTMASK_I2C3 (0x00000004)
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#define INTMASK_I2C4 (0x00000008)
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#define INTMASK_CIRQ1 (0x00000010)
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#define INTMASK_CIRQ2 (0x00000020)
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#define INTMASK_CIRQ3 (0x00000040)
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#define INTMASK_CIRQ4 (0x00000080)
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#define INTMASK_TSINPUT1 (0x00000100)
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#define INTMASK_TSINPUT2 (0x00000200)
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#define INTMASK_TSINPUT3 (0x00000400)
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#define INTMASK_TSINPUT4 (0x00000800)
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#define INTMASK_TSINPUT5 (0x00001000)
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#define INTMASK_TSINPUT6 (0x00002000)
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#define INTMASK_TSINPUT7 (0x00004000)
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#define INTMASK_TSINPUT8 (0x00008000)
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#define INTMASK_TSOUTPUT1 (0x00010000)
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#define INTMASK_TSOUTPUT2 (0x00020000)
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#define INTMASK_TSOUTPUT3 (0x00040000)
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#define INTMASK_TSOUTPUT4 (0x00080000)
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// --------------------------------------------------------------------------
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// I2C Master Controller
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#define I2C_BASE (0x80) // Byte offset
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#define I2C_COMMAND (0x00)
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#define I2C_TIMING (0x04)
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#define I2C_TASKLENGTH (0x08) // High read, low write
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#define I2C_TASKADDRESS (0x0C) // High read, low write
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#define I2C_MONITOR (0x1C)
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#define I2C_BASE_1 (I2C_BASE + 0x00)
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#define I2C_BASE_2 (I2C_BASE + 0x20)
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#define I2C_BASE_3 (I2C_BASE + 0x40)
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#define I2C_BASE_4 (I2C_BASE + 0x60)
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#define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20)
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#define I2C_TASKMEM_BASE (0x1000) // Byte offset
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#define I2C_TASKMEM_SIZE (0x1000)
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#define I2C_SPEED_400 (0x04030404)
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#define I2C_SPEED_200 (0x09080909)
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#define I2C_SPEED_154 (0x0C0B0C0C)
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#define I2C_SPEED_100 (0x13121313)
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#define I2C_SPEED_77 (0x19181919)
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#define I2C_SPEED_50 (0x27262727)
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// --------------------------------------------------------------------------
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// DMA Controller
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#define DMA_BASE_WRITE (0x100)
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#define DMA_BASE_READ (0x140)
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#define DMA_CONTROL (0x00) // 64
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#define DMA_ERROR (0x04) // 65 ( only read instance )
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#define DMA_DIAG_CONTROL (0x1C) // 71
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#define DMA_DIAG_PACKETCOUNTER_LOW (0x20) // 72
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#define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) // 73
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#define DMA_DIAG_TIMECOUNTER_LOW (0x28) // 74
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#define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) // 75
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#define DMA_DIAG_RECHECKCOUNTER (0x30) // 76 ( Split completions on read )
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#define DMA_DIAG_WAITTIMEOUTINIT (0x34) // 77
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#define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) // 78
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#define DMA_DIAG_WAITCOUNTER (0x3C) // 79
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// --------------------------------------------------------------------------
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// DMA Buffer
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#define TS_INPUT_BASE (0x200)
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#define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00)
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#define TS_OUTPUT_BASE (0x280)
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#define TS_OUTPUT_CONTROL(i) (TS_OUTPUT_BASE + (i) * 16 + 0x00)
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#define DMA_BUFFER_BASE (0x300)
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#define DMA_BUFFER_CONTROL(i) (DMA_BUFFER_BASE + (i) * 16 + 0x00)
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#define DMA_BUFFER_ACK(i) (DMA_BUFFER_BASE + (i) * 16 + 0x04)
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#define DMA_BUFFER_CURRENT(i) (DMA_BUFFER_BASE + (i) * 16 + 0x08)
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#define DMA_BUFFER_SIZE(i) (DMA_BUFFER_BASE + (i) * 16 + 0x0c)
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#define DMA_BASE_ADDRESS_TABLE (0x2000)
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#define DMA_BASE_ADDRESS_TABLE_ENTRIES (512)
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187
drivers/media/dvb/ddbridge/ddbridge.h
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187
drivers/media/dvb/ddbridge/ddbridge.h
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@ -0,0 +1,187 @@
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/*
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* ddbridge.h: Digital Devices PCIe bridge driver
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*
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* Copyright (C) 2010-2011 Digital Devices GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 only, as published by the Free Software Foundation.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA
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* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
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*/
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#ifndef _DDBRIDGE_H_
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#define _DDBRIDGE_H_
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/i2c.h>
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#include <linux/mutex.h>
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#include <asm/dma.h>
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#include <linux/dvb/frontend.h>
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#include <linux/dvb/ca.h>
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#include <linux/dvb/video.h>
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#include <linux/dvb/audio.h>
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#include <linux/socket.h>
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#include "dmxdev.h"
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#include "dvbdev.h"
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#include "dvb_demux.h"
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#include "dvb_frontend.h"
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#include "dvb_ringbuffer.h"
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#include "dvb_ca_en50221.h"
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#include "dvb_net.h"
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#include "cxd2099.h"
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#define DDB_MAX_I2C 4
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#define DDB_MAX_PORT 4
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#define DDB_MAX_INPUT 8
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#define DDB_MAX_OUTPUT 4
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struct ddb_info {
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int type;
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#define DDB_NONE 0
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#define DDB_OCTOPUS 1
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char *name;
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int port_num;
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u32 port_type[DDB_MAX_PORT];
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};
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/* DMA_SIZE MUST be divisible by 188 and 128 !!! */
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#define INPUT_DMA_MAX_BUFS 32 /* hardware table limit */
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#define INPUT_DMA_BUFS 8
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#define INPUT_DMA_SIZE (128*47*21)
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#define OUTPUT_DMA_MAX_BUFS 32
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#define OUTPUT_DMA_BUFS 8
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#define OUTPUT_DMA_SIZE (128*47*21)
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struct ddb;
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struct ddb_port;
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struct ddb_input {
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struct ddb_port *port;
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u32 nr;
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int attached;
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dma_addr_t pbuf[INPUT_DMA_MAX_BUFS];
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u8 *vbuf[INPUT_DMA_MAX_BUFS];
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u32 dma_buf_num;
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u32 dma_buf_size;
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struct tasklet_struct tasklet;
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spinlock_t lock;
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wait_queue_head_t wq;
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int running;
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u32 stat;
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u32 cbuf;
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u32 coff;
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struct dvb_adapter adap;
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struct dvb_device *dev;
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struct dvb_frontend *fe;
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struct dvb_frontend *fe2;
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struct dmxdev dmxdev;
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struct dvb_demux demux;
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struct dvb_net dvbnet;
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struct dmx_frontend hw_frontend;
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struct dmx_frontend mem_frontend;
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int users;
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int (*gate_ctrl)(struct dvb_frontend *, int);
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};
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struct ddb_output {
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struct ddb_port *port;
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u32 nr;
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dma_addr_t pbuf[OUTPUT_DMA_MAX_BUFS];
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u8 *vbuf[OUTPUT_DMA_MAX_BUFS];
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u32 dma_buf_num;
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u32 dma_buf_size;
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struct tasklet_struct tasklet;
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spinlock_t lock;
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wait_queue_head_t wq;
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int running;
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u32 stat;
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u32 cbuf;
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u32 coff;
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struct dvb_adapter adap;
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struct dvb_device *dev;
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};
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struct ddb_i2c {
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struct ddb *dev;
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u32 nr;
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struct i2c_adapter adap;
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struct i2c_adapter adap2;
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u32 regs;
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u32 rbuf;
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u32 wbuf;
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int done;
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wait_queue_head_t wq;
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};
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struct ddb_port {
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struct ddb *dev;
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u32 nr;
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struct ddb_i2c *i2c;
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struct mutex i2c_gate_lock;
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u32 class;
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#define DDB_PORT_NONE 0
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#define DDB_PORT_CI 1
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#define DDB_PORT_TUNER 2
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u32 type;
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#define DDB_TUNER_NONE 0
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#define DDB_TUNER_DVBS_ST 1
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#define DDB_TUNER_DVBS_ST_AA 2
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#define DDB_TUNER_DVBCT_TR 16
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#define DDB_TUNER_DVBCT_ST 17
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u32 adr;
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struct ddb_input *input[2];
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struct ddb_output *output;
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struct dvb_ca_en50221 *en;
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};
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struct ddb {
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struct pci_dev *pdev;
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unsigned char *regs;
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struct ddb_port port[DDB_MAX_PORT];
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struct ddb_i2c i2c[DDB_MAX_I2C];
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struct ddb_input input[DDB_MAX_INPUT];
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struct ddb_output output[DDB_MAX_OUTPUT];
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struct device *ddb_dev;
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int nr;
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u8 iobuf[1028];
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struct ddb_info *info;
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int msi;
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};
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/****************************************************************************/
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#define ddbwritel(_val, _adr) writel((_val), \
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(char *) (dev->regs+(_adr)))
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#define ddbreadl(_adr) readl((char *) (dev->regs+(_adr)))
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#define ddbcpyto(_adr,_src,_count) memcpy_toio((char *) \
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(dev->regs+(_adr)),(_src),(_count))
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#define ddbcpyfrom(_dst,_adr,_count) memcpy_fromio((_dst),(char *) \
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(dev->regs+(_adr)),(_count))
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/****************************************************************************/
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#endif
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