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drm/tegra: sor - Remove pixel clock rounding 

The code currently rounds up the clock to the next MHZ, which is
rounding up a 69.5MHz clock to 70MHz on my machine. This in turn
prevents the display from syncing. Removing this rounding fixes eDP
for me.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
hifive-unleashed-5.1
Stéphane Marchesin 2014-05-22 20:32:46 -07:00 committed by Thierry Reding
parent 1b0c7b4840
commit ccb8b12c4b
1 changed files with 0 additions and 3 deletions
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3
drivers/gpu/drm/tegra/sor.c
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@ -876,9 +876,6 @@ static int tegra_output_sor_setup_clock(struct tegra_output *output,
struct tegra_sor *sor = to_sor(output);
int err;
/* round to next MHz */
pclk = DIV_ROUND_UP(pclk, 1000000) * 1000000;
err = clk_set_parent(clk, sor->clk_parent);
if (err < 0) {
dev_err(sor->dev, "failed to set parent clock: %d\n", err);