sh: Encode L1/L2 cache shape in auxvt.
This adds in the L1I/L1D/L2 cache shape support to their respective entries in the ELF auxvt, based on the Alpha implementation. We use this on the userspace libc side for calculating a tightly packed SHMLBA amongst other things. Signed-off-by: Paul Mundt <lethal@linux-sh.org>hifive-unleashed-5.1
Paul Mundt
parent
c8c0a1aba9
commit
cd01204b82
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@ -13,6 +13,7 @@
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/log2.h>
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#include <asm/mmu_context.h>
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#include <asm/processor.h>
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#include <asm/uaccess.h>
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@ -20,6 +21,7 @@
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#include <asm/system.h>
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#include <asm/cacheflush.h>
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#include <asm/cache.h>
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#include <asm/elf.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#ifdef CONFIG_SUPERH32
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@ -151,6 +153,27 @@ static void __uses_jump_to_uncached cache_init(void)
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#define cache_init() do { } while (0)
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#endif
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#define CSHAPE(totalsize, linesize, assoc) \
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((totalsize & ~0xff) | (linesize << 4) | assoc)
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#define CACHE_DESC_SHAPE(desc) \
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CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
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static void detect_cache_shape(void)
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{
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l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache);
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if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED)
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l1i_cache_shape = l1d_cache_shape;
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else
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l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache);
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if (current_cpu_data.flags & CPU_HAS_L2_CACHE)
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l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache);
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else
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l2_cache_shape = -1; /* No S-cache */
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}
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#ifdef CONFIG_SH_DSP
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static void __init release_dsp(void)
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{
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@ -237,11 +260,15 @@ asmlinkage void __cpuinit sh_cpu_init(void)
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/* Init the cache */
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cache_init();
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if (raw_smp_processor_id() == 0)
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if (raw_smp_processor_id() == 0) {
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shm_align_mask = max_t(unsigned long,
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current_cpu_data.dcache.way_size - 1,
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PAGE_SIZE - 1);
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/* Boot CPU sets the cache shape */
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detect_cache_shape();
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}
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/* Disable the FPU */
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if (fpu_disabled) {
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printk("FPU Disabled\n");
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@ -26,6 +26,7 @@
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/page.h>
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#include <asm/elf.h>
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#include <asm/sections.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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@ -78,6 +79,8 @@ EXPORT_SYMBOL(memory_start);
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unsigned long memory_end = 0;
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EXPORT_SYMBOL(memory_end);
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int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
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static int __init early_parse_mem(char *p)
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{
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unsigned long size;
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@ -15,4 +15,16 @@
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#define AT_SYSINFO_EHDR 33
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#endif
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/*
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* More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the
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* value is -1, then the cache doesn't exist. Otherwise:
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*
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* bit 0-3: Cache set-associativity; 0 means fully associative.
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* bit 4-7: Log2 of cacheline size.
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* bit 8-31: Size of the entire cache >> 8.
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*/
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#define AT_L1I_CACHESHAPE 34
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#define AT_L1D_CACHESHAPE 35
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#define AT_L2_CACHESHAPE 36
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#endif /* __ASM_SH_AUXVEC_H */
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@ -161,12 +161,25 @@ extern void __kernel_vsyscall;
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#define VDSO_BASE ((unsigned long)current->mm->context.vdso)
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#define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x))
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#define VSYSCALL_AUX_ENT \
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if (vdso_enabled) \
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NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE);
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#else
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#define VSYSCALL_AUX_ENT
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#endif /* CONFIG_VSYSCALL */
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extern int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
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/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
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#define ARCH_DLINFO \
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do { \
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if (vdso_enabled) \
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NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE); \
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/* Optional vsyscall entry */ \
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VSYSCALL_AUX_ENT \
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\
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/* Cache desc */ \
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NEW_AUX_ENT(AT_L1I_CACHESHAPE, l1i_cache_shape); \
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NEW_AUX_ENT(AT_L1D_CACHESHAPE, l1d_cache_shape); \
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NEW_AUX_ENT(AT_L2_CACHESHAPE, l2_cache_shape); \
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} while (0)
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#endif /* CONFIG_VSYSCALL */
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#endif /* __ASM_SH_ELF_H */
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@ -12,7 +12,7 @@
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#include <asm/types.h>
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#include <asm/ptrace.h>
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#define AT_VECTOR_SIZE_ARCH 1 /* entries in ARCH_DLINFO */
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#define AT_VECTOR_SIZE_ARCH 4 /* entries in ARCH_DLINFO */
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#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
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#define __icbi() \
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