Blackfin: punt OTP MMRs
People should not be accessing OTP MMRs directly. They should instead go through the Blackfin ROM helper functions. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -1046,17 +1046,6 @@
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#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
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#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
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/* OTP/FUSE Registers */
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#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
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#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
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#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
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#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
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#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
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#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
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#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
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#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
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/* Security Registers */
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#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
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@ -1066,17 +1055,6 @@
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#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
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#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
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/* OTP Read/Write Data Buffer Registers */
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#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
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#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
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#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
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#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
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#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
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#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
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#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
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#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
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/* These need to be last due to the cdef/linux inter-dependencies */
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#include <asm/irq.h>
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@ -1770,46 +1770,6 @@
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#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
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#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
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/* Bit masks for OTP_CONTROL */
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#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
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#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
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#define nFIEN 0x0
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#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
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#define nFTESTDEC 0x0
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#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
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#define nFWRTEST 0x0
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#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
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#define nFRDEN 0x0
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#define FWREN 0x8000 /* OTP/Fuse Write Enable */
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#define nFWREN 0x0
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/* Bit masks for OTP_BEN */
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#define FBEN 0xffff /* OTP/Fuse Byte Enable */
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/* Bit masks for OTP_STATUS */
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#define FCOMP 0x1 /* OTP/Fuse Access Complete */
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#define nFCOMP 0x0
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#define FERROR 0x2 /* OTP/Fuse Access Error */
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#define nFERROR 0x0
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#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
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#define nMMRGLOAD 0x0
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#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
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#define nMMRGLOCK 0x0
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#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
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#define nFPGMEN 0x0
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/* Bit masks for OTP_TIMING */
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#define USECDIV 0xff /* Micro Second Divider */
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#define READACC 0x7f00 /* Read Access Time */
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#define CPUMPRL 0x38000 /* Charge Pump Release Time */
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#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
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#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
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#define PGMTIME 0xff000000 /* Program Time */
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/* Bit masks for SECURE_SYSSWT */
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#define EMUDABL 0x1 /* Emulation Disable. */
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@ -1063,17 +1063,6 @@
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#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
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#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
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/* OTP/FUSE Registers */
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#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
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#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
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#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
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#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
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#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
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#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
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#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
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#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
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/* Security Registers */
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#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
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@ -1083,17 +1072,6 @@
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#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
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#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
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/* OTP Read/Write Data Buffer Registers */
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#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
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#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
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#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
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#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
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#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
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#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
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#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
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#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
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/* NFC Registers */
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#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
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@ -1783,46 +1783,6 @@
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#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
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#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
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/* Bit masks for OTP_CONTROL */
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#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
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#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
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#define nFIEN 0x0
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#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
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#define nFTESTDEC 0x0
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#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
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#define nFWRTEST 0x0
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#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
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#define nFRDEN 0x0
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#define FWREN 0x8000 /* OTP/Fuse Write Enable */
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#define nFWREN 0x0
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/* Bit masks for OTP_BEN */
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#define FBEN 0xffff /* OTP/Fuse Byte Enable */
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/* Bit masks for OTP_STATUS */
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#define FCOMP 0x1 /* OTP/Fuse Access Complete */
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#define nFCOMP 0x0
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#define FERROR 0x2 /* OTP/Fuse Access Error */
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#define nFERROR 0x0
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#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
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#define nMMRGLOAD 0x0
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#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
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#define nMMRGLOCK 0x0
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#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
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#define nFPGMEN 0x0
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/* Bit masks for OTP_TIMING */
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#define USECDIV 0xff /* Micro Second Divider */
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#define READACC 0x7f00 /* Read Access Time */
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#define CPUMPRL 0x38000 /* Charge Pump Release Time */
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#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
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#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
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#define PGMTIME 0xff000000 /* Program Time */
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/* Bit masks for SECURE_SYSSWT */
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#define EMUDABL 0x1 /* Emulation Disable. */
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@ -2615,17 +2615,6 @@
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#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
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#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
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/* OTP/FUSE Registers */
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#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
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#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
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#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
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#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
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#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
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#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
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#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
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#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
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/* Security Registers */
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#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
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@ -2640,17 +2629,6 @@
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#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
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#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
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/* OTP Read/Write Data Buffer Registers */
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#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
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#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
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#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
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#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
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#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
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#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
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#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
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#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
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/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
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/* legacy definitions */
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@ -2143,36 +2143,6 @@
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#define DPRESCALE 0xf /* Load Counter Register */
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/* Bit masks for OTP_CONTROL */
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#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
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#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
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#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
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#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
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#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
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#define FWREN 0x8000 /* OTP/Fuse Write Enable */
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/* Bit masks for OTP_BEN */
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#define FBEN 0xffff /* OTP/Fuse Byte Enable */
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/* Bit masks for OTP_STATUS */
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#define FCOMP 0x1 /* OTP/Fuse Access Complete */
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#define FERROR 0x2 /* OTP/Fuse Access Error */
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#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
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#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
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#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
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/* Bit masks for OTP_TIMING */
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#define USECDIV 0xff /* Micro Second Divider */
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#define READACC 0x7f00 /* Read Access Time */
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#define CPUMPRL 0x38000 /* Charge Pump Release Time */
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#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
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#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
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#define PGMTIME 0xff000000 /* Program Time */
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/* Bit masks for SECURE_SYSSWT */
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#define EMUDABL 0x1 /* Emulation Disable. */
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