drm/i915: fix up pch pll handling in ->mode_set
We ->mode_set is called we can't just blindly reuse an existing pll since that might be shared with a different, still active pch output. v2: Only update the pll settings when the pch pll is know to be unused, otherwise we can wreak havoc with a running pipe. Which in the case of DP will likely result in a black screen due to loss of link lock. v3: Tighten up the asserts a bit more, especially make sure that the pch pll is still enabled when we try to disable it. This would have caught the bug fixed in this patch. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1427,7 +1427,8 @@ static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
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/* PCH refclock must be enabled first */
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assert_pch_refclk_enabled(dev_priv);
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if (pll->active++ && pll->on) {
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if (pll->active++) {
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WARN_ON(!pll->on);
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assert_pch_pll_enabled(dev_priv, pll, NULL);
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return;
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}
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@ -1468,10 +1469,9 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
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return;
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}
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if (--pll->active) {
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assert_pch_pll_enabled(dev_priv, pll, NULL);
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assert_pch_pll_enabled(dev_priv, pll, NULL);
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if (--pll->active)
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return;
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}
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DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
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@ -3081,9 +3081,9 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
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pll = intel_crtc->pch_pll;
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if (pll) {
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DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
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DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
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intel_crtc->base.base.id, pll->pll_reg);
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goto prepare;
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intel_put_pch_pll(intel_crtc);
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}
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if (HAS_PCH_IBX(dev_priv->dev)) {
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@ -3128,19 +3128,22 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
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found:
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intel_crtc->pch_pll = pll;
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pll->refcount++;
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DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
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prepare: /* separate function? */
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DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
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if (pll->active == 0) {
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DRM_DEBUG_DRIVER("setting up pll %d\n", i);
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WARN_ON(pll->on);
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assert_pch_pll_disabled(dev_priv, pll, NULL);
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/* Wait for the clocks to stabilize before rewriting the regs */
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I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
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POSTING_READ(pll->pll_reg);
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udelay(150);
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/* Wait for the clocks to stabilize before rewriting the regs */
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I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
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POSTING_READ(pll->pll_reg);
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udelay(150);
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I915_WRITE(pll->fp0_reg, fp);
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I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
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}
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pll->refcount++;
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I915_WRITE(pll->fp0_reg, fp);
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I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
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pll->on = false;
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return pll;
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}
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