i2c: imx: add DMA support for freescale i2c driver
Add dma support for i2c. This function depend on DMA driver. You can turn on it by write both the dmas and dma-name properties in dts node. DMA is optional, even DMA request unsuccessfully, i2c can also work well. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>hifive-unleashed-5.1
Yao Yuan
Wolfram Sang
parent
2fbed5119d
commit
ce1a78840f
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@ -11,6 +11,8 @@ Required properties:
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Optional properties:
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- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
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The absence of the propoerty indicates the default frequency 100 kHz.
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- dmas: A list of two dma specifiers, one for each entry in dma-names.
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- dma-names: should contain "tx" and "rx".
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Examples:
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@ -26,3 +28,12 @@ i2c@70038000 { /* HS-I2C on i.MX51 */
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interrupts = <64>;
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clock-frequency = <400000>;
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};
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i2c0: i2c@40066000 { /* i2c0 on vf610 */
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compatible = "fsl,vf610-i2c";
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reg = <0x40066000 0x1000>;
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interrupts =<0 71 0x04>;
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dmas = <&edma0 0 50>,
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<&edma0 0 51>;
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dma-names = "rx","tx";
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};
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@ -33,7 +33,11 @@
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*******************************************************************************/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/dmapool.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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@ -44,6 +48,7 @@
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <linux/platform_data/i2c-imx.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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@ -58,6 +63,15 @@
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/* Default value */
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#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
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/*
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* Enable DMA if transfer byte size is bigger than this threshold.
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* As the hardware request, it must bigger than 4 bytes.\
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* I have set '16' here, maybe it's not the best but I think it's
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* the appropriate.
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*/
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#define DMA_THRESHOLD 16
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#define DMA_TIMEOUT 1000
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/* IMX I2C registers:
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* the I2C register offset is different between SoCs,
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* to provid support for all these chips, split the
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@ -83,6 +97,7 @@
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#define I2SR_IBB 0x20
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#define I2SR_IAAS 0x40
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#define I2SR_ICF 0x80
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#define I2CR_DMAEN 0x02
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#define I2CR_RSTA 0x04
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#define I2CR_TXAK 0x08
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#define I2CR_MTX 0x10
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@ -169,6 +184,17 @@ struct imx_i2c_hwdata {
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unsigned i2cr_ien_opcode;
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};
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struct imx_i2c_dma {
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struct dma_chan *chan_tx;
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struct dma_chan *chan_rx;
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struct dma_chan *chan_using;
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struct completion cmd_complete;
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dma_addr_t dma_buf;
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unsigned int dma_len;
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enum dma_transfer_direction dma_transfer_dir;
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enum dma_data_direction dma_data_dir;
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};
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struct imx_i2c_struct {
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struct i2c_adapter adapter;
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struct clk *clk;
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@ -181,6 +207,8 @@ struct imx_i2c_struct {
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unsigned int cur_clk;
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unsigned int bitrate;
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const struct imx_i2c_hwdata *hwdata;
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struct imx_i2c_dma *dma;
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};
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static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
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@ -251,6 +279,138 @@ static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
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return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
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}
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/* Functions for DMA support */
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static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
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dma_addr_t phy_addr)
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{
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struct imx_i2c_dma *dma;
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struct dma_slave_config dma_sconfig;
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struct device *dev = &i2c_imx->adapter.dev;
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int ret;
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dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
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if (!dma)
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return;
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dma->chan_tx = dma_request_slave_channel(dev, "tx");
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if (!dma->chan_tx) {
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dev_dbg(dev, "can't request DMA tx channel\n");
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ret = -ENODEV;
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goto fail_al;
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}
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dma_sconfig.dst_addr = phy_addr +
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(IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
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dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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dma_sconfig.dst_maxburst = 1;
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dma_sconfig.direction = DMA_MEM_TO_DEV;
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ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
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if (ret < 0) {
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dev_dbg(dev, "can't configure tx channel\n");
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goto fail_tx;
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}
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dma->chan_rx = dma_request_slave_channel(dev, "rx");
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if (!dma->chan_rx) {
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dev_dbg(dev, "can't request DMA rx channel\n");
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ret = -ENODEV;
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goto fail_tx;
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}
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dma_sconfig.src_addr = phy_addr +
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(IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
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dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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dma_sconfig.src_maxburst = 1;
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dma_sconfig.direction = DMA_DEV_TO_MEM;
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ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
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if (ret < 0) {
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dev_dbg(dev, "can't configure rx channel\n");
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goto fail_rx;
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}
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i2c_imx->dma = dma;
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init_completion(&dma->cmd_complete);
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dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
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dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
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return;
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fail_rx:
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dma_release_channel(dma->chan_rx);
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fail_tx:
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dma_release_channel(dma->chan_tx);
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fail_al:
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devm_kfree(dev, dma);
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dev_info(dev, "can't use DMA\n");
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}
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static void i2c_imx_dma_callback(void *arg)
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{
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struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
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struct imx_i2c_dma *dma = i2c_imx->dma;
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dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
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dma->dma_len, dma->dma_data_dir);
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complete(&dma->cmd_complete);
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}
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static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
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struct i2c_msg *msgs)
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{
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struct imx_i2c_dma *dma = i2c_imx->dma;
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struct dma_async_tx_descriptor *txdesc;
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struct device *dev = &i2c_imx->adapter.dev;
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struct device *chan_dev = dma->chan_using->device->dev;
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dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
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dma->dma_len, dma->dma_data_dir);
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if (dma_mapping_error(chan_dev, dma->dma_buf)) {
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dev_err(dev, "DMA mapping failed\n");
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goto err_map;
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}
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txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
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dma->dma_len, dma->dma_transfer_dir,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!txdesc) {
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dev_err(dev, "Not able to get desc for DMA xfer\n");
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goto err_desc;
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}
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txdesc->callback = i2c_imx_dma_callback;
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txdesc->callback_param = i2c_imx;
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if (dma_submit_error(dmaengine_submit(txdesc))) {
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dev_err(dev, "DMA submit failed\n");
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goto err_submit;
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}
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dma_async_issue_pending(dma->chan_using);
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return 0;
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err_submit:
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err_desc:
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dma_unmap_single(chan_dev, dma->dma_buf,
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dma->dma_len, dma->dma_data_dir);
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err_map:
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return -EINVAL;
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}
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static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
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{
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struct imx_i2c_dma *dma = i2c_imx->dma;
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dma->dma_buf = 0;
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dma->dma_len = 0;
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dma_release_channel(dma->chan_tx);
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dma->chan_tx = NULL;
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dma_release_channel(dma->chan_rx);
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dma->chan_rx = NULL;
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dma->chan_using = NULL;
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}
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/** Functions for IMX I2C adapter driver ***************************************
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*******************************************************************************/
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@ -382,6 +542,7 @@ static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
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i2c_imx->stopped = 0;
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temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
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temp &= ~I2CR_DMAEN;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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return result;
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}
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@ -395,6 +556,8 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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temp &= ~(I2CR_MSTA | I2CR_MTX);
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if (i2c_imx->dma)
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temp &= ~I2CR_DMAEN;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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}
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if (is_imx1_i2c(i2c_imx)) {
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@ -435,6 +598,159 @@ static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
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return IRQ_NONE;
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}
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static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
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struct i2c_msg *msgs)
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{
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int result;
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unsigned int temp = 0;
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unsigned long orig_jiffies = jiffies;
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struct imx_i2c_dma *dma = i2c_imx->dma;
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struct device *dev = &i2c_imx->adapter.dev;
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dma->chan_using = dma->chan_tx;
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dma->dma_transfer_dir = DMA_MEM_TO_DEV;
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dma->dma_data_dir = DMA_TO_DEVICE;
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dma->dma_len = msgs->len - 1;
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result = i2c_imx_dma_xfer(i2c_imx, msgs);
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if (result)
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return result;
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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temp |= I2CR_DMAEN;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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/*
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* Write slave address.
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* The first byte must be transmitted by the CPU.
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*/
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imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
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reinit_completion(&i2c_imx->dma->cmd_complete);
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result = wait_for_completion_timeout(
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&i2c_imx->dma->cmd_complete,
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msecs_to_jiffies(DMA_TIMEOUT));
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if (result <= 0) {
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dmaengine_terminate_all(dma->chan_using);
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return result ?: -ETIMEDOUT;
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}
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/* Waiting for transfer complete. */
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while (1) {
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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if (temp & I2SR_ICF)
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break;
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if (time_after(jiffies, orig_jiffies +
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msecs_to_jiffies(DMA_TIMEOUT))) {
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dev_dbg(dev, "<%s> Timeout\n", __func__);
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return -ETIMEDOUT;
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}
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schedule();
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}
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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temp &= ~I2CR_DMAEN;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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/* The last data byte must be transferred by the CPU. */
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imx_i2c_write_reg(msgs->buf[msgs->len-1],
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i2c_imx, IMX_I2C_I2DR);
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result = i2c_imx_trx_complete(i2c_imx);
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if (result)
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return result;
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result = i2c_imx_acked(i2c_imx);
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if (result)
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return result;
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return 0;
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}
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static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
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struct i2c_msg *msgs, bool is_lastmsg)
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{
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int result;
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unsigned int temp;
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unsigned long orig_jiffies = jiffies;
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struct imx_i2c_dma *dma = i2c_imx->dma;
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struct device *dev = &i2c_imx->adapter.dev;
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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temp |= I2CR_DMAEN;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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dma->chan_using = dma->chan_rx;
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dma->dma_transfer_dir = DMA_DEV_TO_MEM;
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dma->dma_data_dir = DMA_FROM_DEVICE;
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/* The last two data bytes must be transferred by the CPU. */
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dma->dma_len = msgs->len - 2;
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result = i2c_imx_dma_xfer(i2c_imx, msgs);
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if (result)
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return result;
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reinit_completion(&i2c_imx->dma->cmd_complete);
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result = wait_for_completion_timeout(
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&i2c_imx->dma->cmd_complete,
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msecs_to_jiffies(DMA_TIMEOUT));
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if (result <= 0) {
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dmaengine_terminate_all(dma->chan_using);
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return result ?: -ETIMEDOUT;
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}
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/* waiting for transfer complete. */
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while (1) {
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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if (temp & I2SR_ICF)
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break;
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if (time_after(jiffies, orig_jiffies +
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msecs_to_jiffies(DMA_TIMEOUT))) {
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dev_dbg(dev, "<%s> Timeout\n", __func__);
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return -ETIMEDOUT;
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}
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schedule();
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}
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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temp &= ~I2CR_DMAEN;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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/* read n-1 byte data */
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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temp |= I2CR_TXAK;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
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/* read n byte data */
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result = i2c_imx_trx_complete(i2c_imx);
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if (result)
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return result;
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if (is_lastmsg) {
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/*
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* It must generate STOP before read I2DR to prevent
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* controller from generating another clock cycle
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*/
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dev_dbg(dev, "<%s> clear MSTA\n", __func__);
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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temp &= ~(I2CR_MSTA | I2CR_MTX);
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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i2c_imx_bus_busy(i2c_imx, 0);
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i2c_imx->stopped = 1;
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} else {
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/*
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* For i2c master receiver repeat restart operation like:
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* read -> repeat MSTA -> read/write
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* The controller must set MTX before read the last byte in
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* the first read operation, otherwise the first read cost
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* one extra clock cycle.
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*/
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temp = readb(i2c_imx->base + IMX_I2C_I2CR);
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temp |= I2CR_MTX;
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writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
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}
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msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
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return 0;
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}
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static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
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{
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int i, result;
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|
|
@ -504,6 +820,9 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bo
|
|||
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
|
||||
|
||||
if (i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data)
|
||||
return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
|
||||
|
||||
/* read data */
|
||||
for (i = 0; i < msgs->len; i++) {
|
||||
u8 len = 0;
|
||||
|
|
@ -618,8 +937,12 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
|
|||
#endif
|
||||
if (msgs[i].flags & I2C_M_RD)
|
||||
result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
|
||||
else
|
||||
result = i2c_imx_write(i2c_imx, &msgs[i]);
|
||||
else {
|
||||
if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
|
||||
result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
|
||||
else
|
||||
result = i2c_imx_write(i2c_imx, &msgs[i]);
|
||||
}
|
||||
if (result)
|
||||
goto fail0;
|
||||
}
|
||||
|
|
@ -654,6 +977,7 @@ static int i2c_imx_probe(struct platform_device *pdev)
|
|||
struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
||||
void __iomem *base;
|
||||
int irq, ret;
|
||||
dma_addr_t phy_addr;
|
||||
|
||||
dev_dbg(&pdev->dev, "<%s>\n", __func__);
|
||||
|
||||
|
|
@ -668,6 +992,7 @@ static int i2c_imx_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
phy_addr = (dma_addr_t)res->start;
|
||||
i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
|
||||
if (!i2c_imx)
|
||||
return -ENOMEM;
|
||||
|
|
@ -742,6 +1067,9 @@ static int i2c_imx_probe(struct platform_device *pdev)
|
|||
i2c_imx->adapter.name);
|
||||
dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
|
||||
|
||||
/* Init DMA config if support*/
|
||||
i2c_imx_dma_request(i2c_imx, phy_addr);
|
||||
|
||||
return 0; /* Return OK */
|
||||
|
||||
clk_disable:
|
||||
|
|
@ -757,6 +1085,9 @@ static int i2c_imx_remove(struct platform_device *pdev)
|
|||
dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
|
||||
i2c_del_adapter(&i2c_imx->adapter);
|
||||
|
||||
if (i2c_imx->dma)
|
||||
i2c_imx_dma_free(i2c_imx);
|
||||
|
||||
/* setup chip registers to defaults */
|
||||
imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
|
||||
imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
|
||||
|
|
|
|||
Loading…
Reference in New Issue