[ARM] S3C24XX: Split map.h into plat-s3c24xx and mach-s3c2410
Split the map.h definitions into common S3C24XX code by adding arch/arm/plat-s3c24xx/include/plat/map.h and altering the machine specific header for the S3C24A0. As we add a new <plat/map.h> we move the original one in arch/arm/plat-s3c include directory to be called map-base.h to distinguish the two files. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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@ -13,34 +13,20 @@
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#ifndef __ASM_ARCH_MAP_H
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H
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#include <plat/map-base.h>
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#include <plat/map.h>
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#include <plat/map.h>
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#define S3C2410_ADDR(x) S3C_ADDR(x)
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#define S3C2410_ADDR(x) S3C_ADDR(x)
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/* interrupt controller is the first thing we put in, to make
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* the assembly code for the irq detection easier
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*/
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#define S3C24XX_VA_IRQ S3C_VA_IRQ
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#define S3C2410_PA_IRQ (0x4A000000)
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#define S3C24XX_SZ_IRQ SZ_1M
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/* memory controller registers */
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#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
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#define S3C2410_PA_MEMCTRL (0x48000000)
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#define S3C24XX_SZ_MEMCTRL SZ_1M
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/* USB host controller */
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/* USB host controller */
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#define S3C2410_PA_USBHOST (0x49000000)
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#define S3C2410_PA_USBHOST (0x49000000)
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#define S3C24XX_SZ_USBHOST SZ_1M
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/* DMA controller */
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/* DMA controller */
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#define S3C2410_PA_DMA (0x4B000000)
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#define S3C2410_PA_DMA (0x4B000000)
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#define S3C24XX_SZ_DMA SZ_1M
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#define S3C24XX_SZ_DMA SZ_1M
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/* Clock and Power management */
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/* Clock and Power management */
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#define S3C24XX_VA_CLKPWR S3C_VA_SYS
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#define S3C2410_PA_CLKPWR (0x4C000000)
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#define S3C2410_PA_CLKPWR (0x4C000000)
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#define S3C24XX_SZ_CLKPWR SZ_1M
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/* LCD controller */
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/* LCD controller */
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#define S3C2410_PA_LCD (0x4D000000)
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#define S3C2410_PA_LCD (0x4D000000)
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@ -48,48 +34,12 @@
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/* NAND flash controller */
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/* NAND flash controller */
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#define S3C2410_PA_NAND (0x4E000000)
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#define S3C2410_PA_NAND (0x4E000000)
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#define S3C24XX_SZ_NAND SZ_1M
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/* UARTs */
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#define S3C24XX_VA_UART S3C_VA_UART
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#define S3C2410_PA_UART (0x50000000)
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#define S3C24XX_SZ_UART SZ_1M
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/* Timers */
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#define S3C24XX_VA_TIMER S3C_VA_TIMER
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#define S3C2410_PA_TIMER (0x51000000)
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#define S3C24XX_SZ_TIMER SZ_1M
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/* USB Device port */
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#define S3C2410_PA_USBDEV (0x52000000)
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#define S3C24XX_SZ_USBDEV SZ_1M
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/* Watchdog */
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#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
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#define S3C2410_PA_WATCHDOG (0x53000000)
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#define S3C24XX_SZ_WATCHDOG SZ_1M
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/* IIC hardware controller */
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/* IIC hardware controller */
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#define S3C2410_PA_IIC (0x54000000)
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#define S3C2410_PA_IIC (0x54000000)
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#define S3C24XX_SZ_IIC SZ_1M
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/* IIS controller */
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/* IIS controller */
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#define S3C2410_PA_IIS (0x55000000)
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#define S3C2410_PA_IIS (0x55000000)
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#define S3C24XX_SZ_IIS SZ_1M
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/* GPIO ports */
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/* the calculation for the VA of this must ensure that
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* it is the same distance apart from the UART in the
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* phsyical address space, as the initial mapping for the IO
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* is done as a 1:1 maping. This puts it (currently) at
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* 0xFA800000, which is not in the way of any current mapping
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* by the base system.
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*/
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#define S3C2410_PA_GPIO (0x56000000)
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#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
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#define S3C24XX_SZ_GPIO SZ_1M
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/* RTC */
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/* RTC */
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#define S3C2410_PA_RTC (0x57000000)
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#define S3C2410_PA_RTC (0x57000000)
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@ -97,15 +47,12 @@
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/* ADC */
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/* ADC */
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#define S3C2410_PA_ADC (0x58000000)
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#define S3C2410_PA_ADC (0x58000000)
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#define S3C24XX_SZ_ADC SZ_1M
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/* SPI */
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/* SPI */
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#define S3C2410_PA_SPI (0x59000000)
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#define S3C2410_PA_SPI (0x59000000)
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#define S3C24XX_SZ_SPI SZ_1M
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/* SDI */
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/* SDI */
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#define S3C2410_PA_SDI (0x5A000000)
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#define S3C2410_PA_SDI (0x5A000000)
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#define S3C24XX_SZ_SDI SZ_1M
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/* CAMIF */
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/* CAMIF */
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#define S3C2440_PA_CAMIF (0x4F000000)
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#define S3C2440_PA_CAMIF (0x4F000000)
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@ -120,13 +67,6 @@
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#define S3C2443_PA_HSMMC (0x4A800000)
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#define S3C2443_PA_HSMMC (0x4A800000)
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#define S3C2443_SZ_HSMMC (256)
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#define S3C2443_SZ_HSMMC (256)
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/* ISA style IO, for each machine to sort out mappings for, if it
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* implements it. We reserve two 16M regions for ISA.
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*/
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#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
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#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
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/* physical addresses of all the chip-select areas */
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/* physical addresses of all the chip-select areas */
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#define S3C2410_CS0 (0x00000000)
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#define S3C2410_CS0 (0x00000000)
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@ -158,21 +98,7 @@
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#define S3C24XX_PA_RTC S3C2410_PA_RTC
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#define S3C24XX_PA_RTC S3C2410_PA_RTC
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#define S3C24XX_PA_ADC S3C2410_PA_ADC
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#define S3C24XX_PA_ADC S3C2410_PA_ADC
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#define S3C24XX_PA_SPI S3C2410_PA_SPI
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#define S3C24XX_PA_SPI S3C2410_PA_SPI
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#define S3C24XX_PA_SDI S3C2410_PA_SDI
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/* deal with the registers that move under the 2412/2413 */
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#define S3C24XX_PA_NAND S3C2410_PA_NAND
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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#ifndef __ASSEMBLY__
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extern void __iomem *s3c24xx_va_gpio2;
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#endif
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#ifdef CONFIG_CPU_S3C2412_ONLY
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#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
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#else
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#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
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#endif
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#else
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#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
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#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
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#endif
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#endif /* __ASM_ARCH_MAP_H */
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#endif /* __ASM_ARCH_MAP_H */
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@ -14,6 +14,9 @@
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#ifndef __ASM_ARCH_24A0_MAP_H
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#ifndef __ASM_ARCH_24A0_MAP_H
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#define __ASM_ARCH_24A0_MAP_H __FILE__
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#define __ASM_ARCH_24A0_MAP_H __FILE__
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#include <plat/map-base.h>
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#include <plat/map.h>
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#define S3C24A0_PA_IO_BASE (0x40000000)
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#define S3C24A0_PA_IO_BASE (0x40000000)
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#define S3C24A0_PA_CLKPWR (0x40000000)
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#define S3C24A0_PA_CLKPWR (0x40000000)
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#define S3C24A0_PA_IRQ (0x40200000)
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#define S3C24A0_PA_IRQ (0x40200000)
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@ -74,5 +77,7 @@
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#define S3C24XX_PA_RTC S3C24A0_PA_RTC
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#define S3C24XX_PA_RTC S3C24A0_PA_RTC
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#define S3C24XX_PA_ADC S3C24A0_PA_ADC
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#define S3C24XX_PA_ADC S3C24A0_PA_ADC
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#define S3C24XX_PA_SPI S3C24A0_PA_SPI
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#define S3C24XX_PA_SPI S3C24A0_PA_SPI
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#define S3C24XX_PA_SDI S3C24A0_PA_SDI
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#define S3C24XX_PA_NAND S3C24A0_PA_NAND
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#endif /* __ASM_ARCH_24A0_MAP_H */
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#endif /* __ASM_ARCH_24A0_MAP_H */
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@ -192,8 +192,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
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static struct resource s3c_nand_resource[] = {
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static struct resource s3c_nand_resource[] = {
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[0] = {
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[0] = {
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.start = S3C2410_PA_NAND,
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.start = S3C24XX_PA_NAND,
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.end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
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.end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_MEM,
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}
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}
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};
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};
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@ -382,8 +382,8 @@ struct platform_device s3c_device_adc = {
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static struct resource s3c_sdi_resource[] = {
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static struct resource s3c_sdi_resource[] = {
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[0] = {
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[0] = {
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.start = S3C2410_PA_SDI,
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.start = S3C24XX_PA_SDI,
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.end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
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.end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_MEM,
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},
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},
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[1] = {
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[1] = {
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99
arch/arm/plat-s3c24xx/include/plat/map.h
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arch/arm/plat-s3c24xx/include/plat/map.h
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/* linux/include/asm-arm/plat-s3c24xx/map.h
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*
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* Copyright (c) 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_S3C24XX_MAP_H
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#define __ASM_PLAT_S3C24XX_MAP_H
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/* interrupt controller is the first thing we put in, to make
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* the assembly code for the irq detection easier
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*/
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#define S3C24XX_VA_IRQ S3C_VA_IRQ
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#define S3C2410_PA_IRQ (0x4A000000)
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#define S3C24XX_SZ_IRQ SZ_1M
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/* memory controller registers */
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#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
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#define S3C2410_PA_MEMCTRL (0x48000000)
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#define S3C24XX_SZ_MEMCTRL SZ_1M
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/* UARTs */
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#define S3C24XX_VA_UART S3C_VA_UART
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#define S3C2410_PA_UART (0x50000000)
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#define S3C24XX_SZ_UART SZ_1M
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/* Timers */
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#define S3C24XX_VA_TIMER S3C_VA_TIMER
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#define S3C2410_PA_TIMER (0x51000000)
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#define S3C24XX_SZ_TIMER SZ_1M
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/* Clock and Power management */
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#define S3C24XX_VA_CLKPWR S3C_VA_SYS
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#define S3C24XX_SZ_CLKPWR SZ_1M
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/* USB Device port */
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#define S3C2410_PA_USBDEV (0x52000000)
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#define S3C24XX_SZ_USBDEV SZ_1M
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/* Watchdog */
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#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
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#define S3C2410_PA_WATCHDOG (0x53000000)
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#define S3C24XX_SZ_WATCHDOG SZ_1M
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/* Standard size definitions for peripheral blocks. */
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#define S3C24XX_SZ_IIC SZ_1M
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#define S3C24XX_SZ_IIS SZ_1M
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#define S3C24XX_SZ_ADC SZ_1M
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#define S3C24XX_SZ_SPI SZ_1M
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#define S3C24XX_SZ_SDI SZ_1M
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#define S3C24XX_SZ_NAND SZ_1M
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#define S3C24XX_SZ_USBHOST SZ_1M
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/* GPIO ports */
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/* the calculation for the VA of this must ensure that
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* it is the same distance apart from the UART in the
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* phsyical address space, as the initial mapping for the IO
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* is done as a 1:1 maping. This puts it (currently) at
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* 0xFA800000, which is not in the way of any current mapping
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* by the base system.
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*/
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#define S3C2410_PA_GPIO (0x56000000)
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#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
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#define S3C24XX_SZ_GPIO SZ_1M
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/* ISA style IO, for each machine to sort out mappings for, if it
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* implements it. We reserve two 16M regions for ISA.
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*/
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#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
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#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
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/* deal with the registers that move under the 2412/2413 */
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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#ifndef __ASSEMBLY__
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extern void __iomem *s3c24xx_va_gpio2;
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#endif
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#ifdef CONFIG_CPU_S3C2412_ONLY
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#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
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#else
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#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
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#endif
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#else
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#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
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#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
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#endif
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#endif /* __ASM_PLAT_S3C24XX_MAP_H */
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