PCI: altera: Move retrain from fixup to altera_pcie_host_init()
Previously we used a PCI early fixup to initiate a link retrain on Altera devices. But Altera PCIe IP can be configured as either a Root Port or an Endpoint, and they might have same vendor ID, so the fixup would be run for both. We only want to initiate a link retrain for Altera Root Port devices, not for Endpoints, so move the link retrain functionality from the fixup to altera_pcie_host_init(). [bhelgaas: changelog] Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -43,6 +43,7 @@
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#define RP_LTSSM_MASK 0x1f
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#define LTSSM_L0 0xf
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#define PCIE_CAP_OFFSET 0x80
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/* TLP configuration type 0 and 1 */
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#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
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#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
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@ -100,66 +101,6 @@ static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
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return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
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}
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static void altera_wait_link_retrain(struct pci_dev *dev)
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{
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u16 reg16;
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unsigned long start_jiffies;
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struct altera_pcie *pcie = dev->bus->sysdata;
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/* Wait for link training end. */
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start_jiffies = jiffies;
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for (;;) {
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pcie_capability_read_word(dev, PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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break;
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if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
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dev_err(&pcie->pdev->dev, "link retrain timeout\n");
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break;
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}
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udelay(100);
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}
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/* Wait for link is up */
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start_jiffies = jiffies;
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for (;;) {
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if (altera_pcie_link_is_up(pcie))
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break;
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if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
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dev_err(&pcie->pdev->dev, "link up timeout\n");
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break;
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}
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udelay(100);
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}
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}
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static void altera_pcie_retrain(struct pci_dev *dev)
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{
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u16 linkcap, linkstat;
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struct altera_pcie *pcie = dev->bus->sysdata;
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if (!altera_pcie_link_is_up(pcie))
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return;
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/*
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* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
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* current speed is 2.5 GB/s.
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*/
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pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
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if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
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return;
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pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
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if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
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pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_RL);
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altera_wait_link_retrain(dev);
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}
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}
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DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
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/*
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* Altera PCIe port uses BAR0 of RC's configuration space as the translation
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* from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
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@ -434,6 +375,90 @@ static struct pci_ops altera_pcie_ops = {
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.write = altera_pcie_cfg_write,
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};
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static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
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unsigned int devfn, int offset, u16 *value)
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{
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u32 data;
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int ret;
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ret = _altera_pcie_cfg_read(pcie, busno, devfn,
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PCIE_CAP_OFFSET + offset, sizeof(*value),
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&data);
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*value = data;
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return ret;
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}
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static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
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unsigned int devfn, int offset, u16 value)
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{
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return _altera_pcie_cfg_write(pcie, busno, devfn,
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PCIE_CAP_OFFSET + offset, sizeof(value),
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value);
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}
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static void altera_wait_link_retrain(struct altera_pcie *pcie)
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{
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u16 reg16;
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unsigned long start_jiffies;
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/* Wait for link training end. */
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start_jiffies = jiffies;
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for (;;) {
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altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
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PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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break;
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if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
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dev_err(&pcie->pdev->dev, "link retrain timeout\n");
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break;
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}
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udelay(100);
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}
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/* Wait for link is up */
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start_jiffies = jiffies;
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for (;;) {
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if (altera_pcie_link_is_up(pcie))
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break;
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if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
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dev_err(&pcie->pdev->dev, "link up timeout\n");
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break;
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}
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udelay(100);
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}
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}
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static void altera_pcie_retrain(struct altera_pcie *pcie)
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{
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u16 linkcap, linkstat, linkctl;
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if (!altera_pcie_link_is_up(pcie))
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return;
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/*
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* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
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* current speed is 2.5 GB/s.
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*/
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altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
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&linkcap);
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if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
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return;
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altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
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&linkstat);
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if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
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altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
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PCI_EXP_LNKCTL, &linkctl);
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linkctl |= PCI_EXP_LNKCTL_RL;
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altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
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PCI_EXP_LNKCTL, linkctl);
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altera_wait_link_retrain(pcie);
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}
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}
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static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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@ -555,6 +580,11 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie)
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return 0;
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}
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static void altera_pcie_host_init(struct altera_pcie *pcie)
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{
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altera_pcie_retrain(pcie);
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}
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static int altera_pcie_probe(struct platform_device *pdev)
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{
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struct altera_pcie *pcie;
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@ -592,6 +622,7 @@ static int altera_pcie_probe(struct platform_device *pdev)
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cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
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/* enable all interrupts */
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cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
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altera_pcie_host_init(pcie);
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bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
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pcie, &pcie->resources);
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