ARM: l2x0/pl310: Refactor Kconfig to be more maintainable
Making CACHE_L2X0 depend on (huge list of MACH_ and ARCH_ configs)
is bothersome to maintain and likely to lead to merge conflicts.
This patch moves the knowledge of which platforms have a L2x0 or
PL310 cache controller to the individual machines. To enable this,
a new MIGHT_HAVE_CACHE_L2X0 config option is introduced to allow
machines to indicate that they may have such a cache controller
independently of each other.
Boards/SoCs which cannot reliably operate without the L2 cache
controller support will need to select CACHE_L2X0 directly from
their own Kconfigs instead. This applies to some TrustZone-enabled
boards where Linux runs in the Normal World, for example.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
(for cns3xxx)
Acked-by: Tony Lindgren <tony@atomide.com>
(for omap)
Acked-by: Shawn Guo <shawn.guo@linaro.org>
(for imx)
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
(for exynos)
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
(for imx)
Acked-by: Olof Johansson <olof@lixom.net>
(for tegra)
hifive-unleashed-5.1
Dave Martin
parent
caca6a03d3
commit
ce5ea9f376
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@ -344,6 +344,7 @@ config ARCH_HIGHBANK
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select CPU_V7
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select GENERIC_CLOCKEVENTS
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select HAVE_ARM_SCU
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select MIGHT_HAVE_CACHE_L2X0
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select USE_OF
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help
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Support for the Calxeda Highbank SoC based boards.
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@ -361,6 +362,7 @@ config ARCH_CNS3XXX
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select CPU_V6K
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select GENERIC_CLOCKEVENTS
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select ARM_GIC
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select MIGHT_HAVE_CACHE_L2X0
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select MIGHT_HAVE_PCI
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select PCI_DOMAINS if PCI
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help
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@ -381,6 +383,7 @@ config ARCH_PRIMA2
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select GENERIC_CLOCKEVENTS
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select CLKDEV_LOOKUP
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select GENERIC_IRQ_CHIP
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select MIGHT_HAVE_CACHE_L2X0
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select USE_OF
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select ZONE_DMA
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help
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@ -633,6 +636,7 @@ config ARCH_TEGRA
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select GENERIC_GPIO
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select HAVE_CLK
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select HAVE_SCHED_CLOCK
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select MIGHT_HAVE_CACHE_L2X0
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select ARCH_HAS_CPUFREQ
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help
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This enables support for NVIDIA Tegra based systems (Tegra APX,
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@ -703,6 +707,7 @@ config ARCH_SHMOBILE
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select CLKDEV_LOOKUP
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select HAVE_MACH_CLKDEV
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select GENERIC_CLOCKEVENTS
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select MIGHT_HAVE_CACHE_L2X0
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select NO_IOPORT
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select SPARSE_IRQ
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select MULTI_IRQ_HANDLER
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@ -904,6 +909,7 @@ config ARCH_U8500
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select CLKDEV_LOOKUP
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_HAS_CPUFREQ
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select MIGHT_HAVE_CACHE_L2X0
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help
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Support for ST-Ericsson's Ux500 architecture
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@ -914,6 +920,7 @@ config ARCH_NOMADIK
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select CPU_ARM926T
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select CLKDEV_LOOKUP
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select GENERIC_CLOCKEVENTS
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select MIGHT_HAVE_CACHE_L2X0
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select ARCH_REQUIRE_GPIOLIB
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help
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Support for the Nomadik platform by ST-Ericsson
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@ -973,6 +980,7 @@ config ARCH_ZYNQ
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select ARM_GIC
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select ARM_AMBA
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select ICST
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select MIGHT_HAVE_CACHE_L2X0
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select USE_OF
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help
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Support for Xilinx Zynq ARM Cortex A9 Platform
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@ -17,6 +17,7 @@ choice
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config ARCH_EXYNOS4
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bool "SAMSUNG EXYNOS4"
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select MIGHT_HAVE_CACHE_L2X0
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help
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Samsung EXYNOS4 SoCs based systems
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@ -44,6 +44,7 @@ config ARCH_OMAP4
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select CPU_V7
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select ARM_GIC
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select LOCAL_TIMERS if SMP
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select MIGHT_HAVE_CACHE_L2X0
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select PL310_ERRATA_588369
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select PL310_ERRATA_727915
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select ARM_ERRATA_720789
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@ -12,6 +12,7 @@ config REALVIEW_EB_A9MP
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bool "Support Multicore Cortex-A9 Tile"
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depends on MACH_REALVIEW_EB
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select CPU_V7
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select MIGHT_HAVE_CACHE_L2X0
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help
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Enable support for the Cortex-A9MPCore tile fitted to the
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Realview(R) Emulation Baseboard platform.
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@ -21,6 +22,7 @@ config REALVIEW_EB_ARM11MP
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depends on MACH_REALVIEW_EB
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select CPU_V6K
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select ARCH_HAS_BARRIERS if SMP
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select MIGHT_HAVE_CACHE_L2X0
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help
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Enable support for the ARM11MPCore tile fitted to the Realview(R)
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Emulation Baseboard platform.
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@ -39,6 +41,7 @@ config MACH_REALVIEW_PB11MP
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select CPU_V6K
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select ARM_GIC
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select HAVE_PATA_PLATFORM
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select MIGHT_HAVE_CACHE_L2X0
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select ARCH_HAS_BARRIERS if SMP
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help
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Include support for the ARM(R) RealView(R) Platform Baseboard for
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@ -51,6 +54,7 @@ config MACH_REALVIEW_PB1176
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select CPU_V6
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select ARM_GIC
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select HAVE_TCM
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select MIGHT_HAVE_CACHE_L2X0
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help
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Include support for the ARM(R) RealView(R) Platform Baseboard for
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ARM1176JZF-S.
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@ -78,6 +82,7 @@ config MACH_REALVIEW_PBX
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bool "Support RealView(R) Platform Baseboard Explore"
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select ARM_GIC
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select HAVE_PATA_PLATFORM
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select MIGHT_HAVE_CACHE_L2X0
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select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
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select ZONE_DMA if SPARSEMEM
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help
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@ -8,5 +8,6 @@ config ARCH_VEXPRESS_CA9X4
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select ARM_ERRATA_720789
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select ARM_ERRATA_751472
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select ARM_ERRATA_753970
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select MIGHT_HAVE_CACHE_L2X0
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endmenu
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@ -816,14 +816,23 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
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Say Y here to use the Feroceon L2 cache in writethrough mode.
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Unless you specifically require this, say N for writeback mode.
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config MIGHT_HAVE_CACHE_L2X0
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bool
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help
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This option should be selected by machines which have a L2x0
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or PL310 cache controller, but where its use is optional.
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The only effect of this option is to make CACHE_L2X0 and
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related options available to the user for configuration.
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Boards or SoCs which always require the cache controller
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support to be present should select CACHE_L2X0 directly
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instead of this option, thus preventing the user from
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inadvertently configuring a broken kernel.
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config CACHE_L2X0
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bool "Enable the L2x0 outer cache controller"
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depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
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REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
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ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
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ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
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ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
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default y
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bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
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default MIGHT_HAVE_CACHE_L2X0
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select OUTER_CACHE
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select OUTER_CACHE_SYNC
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help
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@ -20,6 +20,7 @@ config ARCH_IMX_V6_V7
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bool "i.MX3, i.MX6"
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select AUTO_ZRELADDR if !ZBOOT_ROM
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select ARM_PATCH_PHYS_VIRT
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select MIGHT_HAVE_CACHE_L2X0
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help
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This enables support for systems based on the Freescale i.MX3 and i.MX6
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family.
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