drm/i915: Wait for vblank in hsw_enable_ips()
Now that the vblank wait is gone from intel_enable_primary_plane(), hsw_enable_ips() needs to do the vblank wait itself. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3734,17 +3734,17 @@ static void intel_disable_planes(struct drm_crtc *crtc)
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void hsw_enable_ips(struct intel_crtc *crtc)
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void hsw_enable_ips(struct intel_crtc *crtc)
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{
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (!crtc->config.ips_enabled)
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if (!crtc->config.ips_enabled)
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return;
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return;
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/* We can only enable IPS after we enable a plane and wait for a vblank.
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/* We can only enable IPS after we enable a plane and wait for a vblank */
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* We guarantee that the plane is enabled by calling intel_enable_ips
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intel_wait_for_vblank(dev, crtc->pipe);
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* only after intel_enable_plane. And intel_enable_plane already waits
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* for a vblank, so all we need to do here is to enable the IPS bit. */
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assert_plane_enabled(dev_priv, crtc->plane);
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assert_plane_enabled(dev_priv, crtc->plane);
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if (IS_BROADWELL(crtc->base.dev)) {
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if (IS_BROADWELL(dev)) {
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mutex_lock(&dev_priv->rps.hw_lock);
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mutex_lock(&dev_priv->rps.hw_lock);
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WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
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WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
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mutex_unlock(&dev_priv->rps.hw_lock);
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mutex_unlock(&dev_priv->rps.hw_lock);
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@ -696,10 +696,7 @@ intel_post_enable_primary(struct drm_crtc *crtc)
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* when going from primary only to sprite only and vice
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* when going from primary only to sprite only and vice
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* versa.
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* versa.
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*/
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*/
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if (intel_crtc->config.ips_enabled) {
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hsw_enable_ips(intel_crtc);
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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hsw_enable_ips(intel_crtc);
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}
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mutex_lock(&dev->struct_mutex);
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mutex_lock(&dev->struct_mutex);
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intel_update_fbc(dev);
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intel_update_fbc(dev);
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