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ARM i.MX6Q: Fix IOMUXC GPR1 defines for ENET_CLK_SEL and IPU1/2_MUX 

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
hifive-unleashed-5.1
Philipp Zabel 2013-06-26 15:08:48 +02:00 committed by Shawn Guo
parent 0d5ca6d973
commit ceac9b9214
1 changed files with 8 additions and 8 deletions
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16
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
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@ -103,15 +103,15 @@
#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
#define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21)
#define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0
#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0