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perf/core improvements and fixes:

Browse source 
Infrastructure:
 
 - Do not consider empty files as valid srclines (Milian Wolff)
 
 - Fix wrong size in perf_record_mmap for last kernel module,
   which resulted in erroneous symbol resolution in at least s390x (Thomas Richter)
 
 - Add missing newline to expr parser error messages (Andi Kleen)
 
 - Fix saved values rbtree lookup in 'perf stat' (Andi Kleen)
 
 - Add support for shell based tests in 'perf test', add a few that
   run 'perf probe', 'perf trace', using kprobes, uprobes to check
   the output of those tools and the effects on the system, checking,
   for instance, DWARF backtraces from uprobes (Arnaldo Carvalho de Melo)
 
 Arch specific:
 
 - Add ppc64le to audit uname list in the python scripting support (Naveen N. Rao)
 
 - Update POWER9 vendor events tables (Sukadev Bhattiprolu)
 
 - Fix module symbol adjustment for s390x (Thomas Richter)
 
 Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEELb9bqkb7Te0zijNb1lAW81NSqkAFAlmRzjQACgkQ1lAW81NS
 qkA9FQ/9GCSSigMlbIhqbTDIukKRB9n0dZmU+s7g+SQ+PyLn9tfESfvbOECnfkmy
 Tz9BniiIJyjGEOpj0Du0v/Pb/drsolPppqRV48GkmrcNOC6WULAcJL18q2n53hfE
 U3ku5QXS/6JklocQhXkuLYdtz/iZcfq6aQs67zSVtUKMNV4NiF1k2Yqxki+S/IRZ
 CDZr0s84AHygbwDfyDBtktqeVBO+lcK7dQLbAIj8WjIBjlpIVvOOGJwmwN9vyp71
 jd1+7layrES7wepqfSMD1Vx9feIscpOYT9o2uW41pcYe4f9Q8Tgwh76Yni4d8Dp/
 XPqTQ6PxrDA9duj6QkGL2nBYvFmNLI8dIR7d1Esq5JrRY34hxMzxbzQxFiU7zWvc
 yRV+QBHucjxuwFTu497p/EmqGmMI/t47/YrOCGYHlPOlkVd/T00QzR2XLxXu6CkF
 erzmIGFgFIrJ8WX0YzSABgGZK6RFQa11IcbqlrajlIP8qNo1zCsKPoOGBFSZIw//
 S8lwF98fKBpfcbJ1ptvFwtyiZ2yRJeAk+0RTZn/DA/oe4ewj994TH2JOmdaOz36I
 ssmEAuyh21POvRiSYiYIu/MkUVR5tkqFJu4KQJI42DpUK8DmDatx9mkCNAzAps+d
 apDKEqrmQiSEFD78Ac+ivthC7+FgnaNiSaBIB4rVmtARAS5jBqQ=
 =8FjQ
 -----END PGP SIGNATURE-----

Merge tag 'perf-core-for-mingo-4.14-20170814' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core

Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo:

Infrastructure changes:

- Do not consider empty files as valid srclines (Milian Wolff)

- Fix wrong size in perf_record_mmap for last kernel module,
  which resulted in erroneous symbol resolution in at least s390x (Thomas Richter)

- Add missing newline to expr parser error messages (Andi Kleen)

- Fix saved values rbtree lookup in 'perf stat' (Andi Kleen)

- Add support for shell based tests in 'perf test', add a few that
  run 'perf probe', 'perf trace', using kprobes, uprobes to check
  the output of those tools and the effects on the system, checking,
  for instance, DWARF backtraces from uprobes (Arnaldo Carvalho de Melo)

Arch specific changes:

- Add ppc64le to audit uname list in the python scripting support (Naveen N. Rao)

- Update POWER9 vendor events tables (Sukadev Bhattiprolu)

- Fix module symbol adjustment for s390x (Thomas Richter)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar 2017-08-14 19:38:40 +02:00
parent 82119cbe8e 8fc375d7d3
commit cf31b7dd51
80 changed files with 4989 additions and 3414 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
tools/perf/Makefile.perf
View file

@ -760,7 +760,11 @@ install-tests: all install-gtk
$(INSTALL) -d -m 755 '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests'; \
$(INSTALL) tests/attr.py '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests'; \
$(INSTALL) -d -m 755 '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/attr'; \
$(INSTALL) tests/attr/* '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/attr'
$(INSTALL) tests/attr/* '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/attr'; \
$(INSTALL) -d -m 755 '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell'; \
$(INSTALL) tests/shell/*.sh '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell'; \
$(INSTALL) -d -m 755 '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell/lib'; \
$(INSTALL) tests/shell/lib/*.sh '$(DESTDIR_SQ)$(perfexec_instdir_SQ)/tests/shell/lib'
install-bin: install-tools install-tests install-traceevent-plugins

7
tools/perf/arch/s390/util/sym-handling.c
View file

@ -19,4 +19,11 @@ bool elf__needs_adjust_symbols(GElf_Ehdr ehdr)
return ehdr.e_type == ET_REL || ehdr.e_type == ET_DYN;
}
void arch__adjust_sym_map_offset(GElf_Sym *sym,
GElf_Shdr *shdr __maybe_unused,
struct map *map)
{
if (map->type == MAP__FUNCTION)
sym->st_value += map->start;
}
#endif

11
tools/perf/arch/x86/include/arch-tests.h
View file

@ -1,11 +1,14 @@
#ifndef ARCH_TESTS_H
#define ARCH_TESTS_H
#include <linux/compiler.h>
struct test;
/* Tests */
int test__rdpmc(int subtest);
int test__perf_time_to_tsc(int subtest);
int test__insn_x86(int subtest);
int test__intel_cqm_count_nmi_context(int subtest);
int test__rdpmc(struct test *test __maybe_unused, int subtest);
int test__perf_time_to_tsc(struct test *test __maybe_unused, int subtest);
int test__insn_x86(struct test *test __maybe_unused, int subtest);
int test__intel_cqm_count_nmi_context(struct test *test __maybe_unused, int subtest);
#ifdef HAVE_DWARF_UNWIND_SUPPORT
struct thread;

2
tools/perf/arch/x86/tests/insn-x86.c
View file

@ -171,7 +171,7 @@ static int test_data_set(struct test_data *dat_set, int x86_64)
* verbose (-v) option to see all the instructions and whether or not they
* decoded successfuly.
*/
int test__insn_x86(int subtest __maybe_unused)
int test__insn_x86(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int ret = 0;

2
tools/perf/arch/x86/tests/intel-cqm.c
View file

@ -36,7 +36,7 @@ static pid_t spawn(void)
* the last read counter value to avoid triggering a WARN_ON_ONCE() in
* smp_call_function_many() caused by sending IPIs from NMI context.
*/
int test__intel_cqm_count_nmi_context(int subtest __maybe_unused)
int test__intel_cqm_count_nmi_context(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct perf_evlist *evlist = NULL;
struct perf_evsel *evsel = NULL;

2
tools/perf/arch/x86/tests/perf-time-to-tsc.c
View file

@ -37,7 +37,7 @@
* %0 is returned, otherwise %-1 is returned. If TSC conversion is not
* supported then then the test passes but " (not supported)" is printed.
*/
int test__perf_time_to_tsc(int subtest __maybe_unused)
int test__perf_time_to_tsc(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct record_opts opts = {
.mmap_pages = UINT_MAX,

2
tools/perf/arch/x86/tests/rdpmc.c
View file

@ -154,7 +154,7 @@ out_close:
return 0;
}
int test__rdpmc(int subtest __maybe_unused)
int test__rdpmc(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int status = 0;
int wret = 0;

20
tools/perf/pmu-events/arch/powerpc/mapfile.csv
View file

@ -13,13 +13,13 @@
#
# Power8 entries
004b0000,1,power8.json,core
004b0201,1,power8.json,core
004c0000,1,power8.json,core
004d0000,1,power8.json,core
004d0100,1,power8.json,core
004d0200,1,power8.json,core
004c0100,1,power8.json,core
004e0100,1,power9.json,core
004e0200,1,power9.json,core
004e1200,1,power9.json,core
004b0000,1,power8,core
004b0201,1,power8,core
004c0000,1,power8,core
004d0000,1,power8,core
004d0100,1,power8,core
004d0200,1,power8,core
004c0100,1,power8,core
004e0100,1,power9,core
004e0200,1,power9,core
004e1200,1,power9,core

1 # Format:
13 #
14 # Power8 entries
15 004b0000,1,power8.json,core 004b0000,1,power8,core
16 004b0201,1,power8.json,core 004b0201,1,power8,core
17 004c0000,1,power8.json,core 004c0000,1,power8,core
18 004d0000,1,power8.json,core 004d0000,1,power8,core
19 004d0100,1,power8.json,core 004d0100,1,power8,core
20 004d0200,1,power8.json,core 004d0200,1,power8,core
21 004c0100,1,power8.json,core 004c0100,1,power8,core
22 004e0100,1,power9.json,core 004e0100,1,power9,core
23 004e0200,1,power9.json,core 004e0200,1,power9,core
24 004e1200,1,power9.json,core 004e1200,1,power9,core
25

259
tools/perf/pmu-events/arch/powerpc/power9/cache.json
View file

@ -1,176 +1,137 @@
[
{,
"EventCode": "0x1002A",
"EventName": "PM_CMPLU_STALL_LARX",
"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied",
"PublicDescription": ""
},
{,
"EventCode": "0x1003C",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
"PublicDescription": ""
},
{,
"EventCode": "0x14048",
"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x3E054",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.",
"PublicDescription": ""
},
{,
"EventCode": "0x400F0",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1, at execution time (not gated by finish, which means this counter can be greater than loads finished)",
"PublicDescription": ""
},
{,
"EventCode": "0x1404A",
"EventName": "PM_INST_FROM_RL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x1C058",
"EventName": "PM_DTLB_MISS_16G",
"BriefDescription": "Data TLB Miss page size 16G",
"PublicDescription": ""
},
{,
"EventCode": "0x1D15C",
"EventName": "PM_MRK_DTLB_MISS_1G",
"BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used",
"PublicDescription": ""
"EventCode": "0x300F4",
"EventName": "PM_THRD_CONC_RUN_INST",
"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
},
{,
"EventCode": "0x1E056",
"EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion",
"PublicDescription": ""
},
{,
"EventCode": "0x101E6",
"EventName": "PM_THRESH_EXC_4096",
"BriefDescription": "Threshold counter exceed a count of 4096",
"PublicDescription": ""
},
{,
"EventCode": "0x2C01A",
"EventName": "PM_CMPLU_STALL_LHS",
"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data",
"PublicDescription": ""
},
{,
"EventCode": "0x2D016",
"EventName": "PM_CMPLU_STALL_FXU",
"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
"PublicDescription": ""
},
{,
"EventCode": "0x24046",
"EventName": "PM_INST_FROM_RL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x2404A",
"EventName": "PM_INST_FROM_RL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x2F140",
"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x2D15E",
"EventName": "PM_MRK_DTLB_MISS_16G",
"BriefDescription": "Marked Data TLB Miss page size 16G",
"PublicDescription": ""
},
{,
"EventCode": "0x3F14A",
"EventName": "PM_MRK_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x3D156",
"EventName": "PM_MRK_DTLB_MISS_64K",
"BriefDescription": "Marked Data TLB Miss page size 64K",
"PublicDescription": ""
},
{,
"EventCode": "0x3006C",
"EventName": "PM_RUN_CYC_SMT2_MODE",
"BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode",
"PublicDescription": ""
},
{,
"EventCode": "0x300F4",
"EventName": "PM_THRD_CONC_RUN_INST",
"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set",
"PublicDescription": ""
},
{,
"EventCode": "0x4C014",
"EventName": "PM_CMPLU_STALL_LMQ_FULL",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full",
"PublicDescription": ""
},
{,
"EventCode": "0x4C016",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
"PublicDescription": ""
},
{,
"EventCode": "0x4D014",
"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish",
"PublicDescription": ""
"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion"
},
{,
"EventCode": "0x4D016",
"EventName": "PM_CMPLU_STALL_FXLONG",
"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)",
"PublicDescription": ""
"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)"
},
{,
"EventCode": "0x2D016",
"EventName": "PM_CMPLU_STALL_FXU",
"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
},
{,
"EventCode": "0x1D15C",
"EventName": "PM_MRK_DTLB_MISS_1G",
"BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used"
},
{,
"EventCode": "0x4D12A",
"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
},
{,
"EventCode": "0x4C15E",
"EventName": "PM_MRK_DTLB_MISS_16M",
"BriefDescription": "Marked Data TLB Miss page size 16M",
"PublicDescription": ""
"EventCode": "0x1003C",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
},
{,
"EventCode": "0x401E4",
"EventName": "PM_MRK_DTLB_MISS",
"BriefDescription": "Marked dtlb miss",
"PublicDescription": ""
"EventCode": "0x4C014",
"EventName": "PM_CMPLU_STALL_LMQ_FULL",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full"
},
{,
"EventCode": "0x14048",
"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x4D014",
"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish"
},
{,
"EventCode": "0x2404A",
"EventName": "PM_INST_FROM_RL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x1404A",
"EventName": "PM_INST_FROM_RL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x401EA",
"EventName": "PM_THRESH_EXC_128",
"BriefDescription": "Threshold counter exceeded a value of 128",
"PublicDescription": ""
"BriefDescription": "Threshold counter exceeded a value of 128"
},
{,
"EventCode": "0x400F6",
"EventName": "PM_BR_MPRED_CMPL",
"BriefDescription": "Number of Branch Mispredicts",
"PublicDescription": ""
"BriefDescription": "Number of Branch Mispredicts"
},
{,
"EventCode": "0x2F140",
"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x101E6",
"EventName": "PM_THRESH_EXC_4096",
"BriefDescription": "Threshold counter exceed a count of 4096"
},
{,
"EventCode": "0x3D156",
"EventName": "PM_MRK_DTLB_MISS_64K",
"BriefDescription": "Marked Data TLB Miss page size 64K"
},
{,
"EventCode": "0x4C15E",
"EventName": "PM_MRK_DTLB_MISS_16M",
"BriefDescription": "Marked Data TLB Miss page size 16M"
},
{,
"EventCode": "0x2D15E",
"EventName": "PM_MRK_DTLB_MISS_16G",
"BriefDescription": "Marked Data TLB Miss page size 16G"
},
{,
"EventCode": "0x3F14A",
"EventName": "PM_MRK_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x4C016",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict"
},
{,
"EventCode": "0x2C01A",
"EventName": "PM_CMPLU_STALL_LHS",
"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data"
},
{,
"EventCode": "0x401E4",
"EventName": "PM_MRK_DTLB_MISS",
"BriefDescription": "Marked dtlb miss"
},
{,
"EventCode": "0x24046",
"EventName": "PM_INST_FROM_RL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x1002A",
"EventName": "PM_CMPLU_STALL_LARX",
"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
},
{,
"EventCode": "0x3006C",
"EventName": "PM_RUN_CYC_SMT2_MODE",
"BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode"
},
{,
"EventCode": "0x1C058",
"EventName": "PM_DTLB_MISS_16G",
"BriefDescription": "Data TLB Miss page size 16G"
}
]
]

42
tools/perf/pmu-events/arch/powerpc/power9/floating-point.json
View file

@ -1,44 +1,32 @@
[
{,
"EventCode": "0x10058",
"EventName": "PM_MEM_LOC_THRESH_IFU",
"BriefDescription": "Local Memory above threshold for IFU speculation control",
"PublicDescription": ""
},
{,
"EventCode": "0x4505E",
"EventName": "PM_FLOP_CMPL",
"BriefDescription": "Floating Point Operation Finished",
"PublicDescription": ""
},
{,
"EventCode": "0x1415A",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
"PublicDescription": ""
"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load"
},
{,
"EventCode": "0x10058",
"EventName": "PM_MEM_LOC_THRESH_IFU",
"BriefDescription": "Local Memory above threshold for IFU speculation control"
},
{,
"EventCode": "0x2D028",
"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache",
"PublicDescription": ""
},
{,
"EventCode": "0x2D154",
"EventName": "PM_MRK_DERAT_MISS_64K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K",
"PublicDescription": ""
"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache"
},
{,
"EventCode": "0x30012",
"EventName": "PM_FLUSH_COMPLETION",
"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush",
"PublicDescription": ""
"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush"
},
{,
"EventCode": "0x2D154",
"EventName": "PM_MRK_DERAT_MISS_64K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K"
},
{,
"EventCode": "0x4016E",
"EventName": "PM_THRESH_NOT_MET",
"BriefDescription": "Threshold counter did not meet threshold",
"PublicDescription": ""
"BriefDescription": "Threshold counter did not meet threshold"
}
]
]

757
tools/perf/pmu-events/arch/powerpc/power9/frontend.json
View file

@ -1,446 +1,377 @@
[
{,
"EventCode": "0x20036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "Branches that are not strongly biased",
"PublicDescription": ""
"EventCode": "0x3E15C",
"EventName": "PM_MRK_L2_TM_ST_ABORT_SISTER",
"BriefDescription": "TM marked store abort for this thread"
},
{,
"EventCode": "0x40036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "Branches that are not strongly biased",
"PublicDescription": ""
},
{,
"EventCode": "0x10004",
"EventName": "PM_CMPLU_STALL_LRQ_OTHER",
"BriefDescription": "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others",
"PublicDescription": ""
},
{,
"EventCode": "0x10010",
"EventName": "PM_PMC4_OVERFLOW",
"BriefDescription": "Overflow from counter 4",
"PublicDescription": ""
},
{,
"EventCode": "0x1001A",
"EventName": "PM_LSU_SRQ_FULL_CYC",
"BriefDescription": "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource",
"PublicDescription": ""
},
{,
"EventCode": "0x10020",
"EventName": "PM_PMC4_REWIND",
"BriefDescription": "PMC4 Rewind Event",
"PublicDescription": ""
},
{,
"EventCode": "0x1003A",
"EventName": "PM_CMPLU_STALL_LSU_FIN",
"BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish",
"PublicDescription": ""
},
{,
"EventCode": "0x1013E",
"EventName": "PM_MRK_LD_MISS_EXPOSED_CYC",
"BriefDescription": "Marked Load exposed Miss (use edge detect to count #)",
"PublicDescription": ""
},
{,
"EventCode": "0x1C044",
"EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x15044",
"EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x15046",
"EventName": "PM_IPTEG_FROM_L3.1_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1015E",
"EventName": "PM_MRK_FAB_RSP_RD_T_INTV",
"BriefDescription": "Sampled Read got a T intervention",
"PublicDescription": ""
},
{,
"EventCode": "0x14054",
"EventName": "PM_INST_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch",
"PublicDescription": ""
},
{,
"EventCode": "0x15152",
"EventName": "PM_SYNC_MRK_BR_LINK",
"BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt",
"PublicDescription": ""
},
{,
"EventCode": "0x1515C",
"EventName": "PM_SYNC_MRK_BR_MPRED",
"BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt",
"PublicDescription": ""
},
{,
"EventCode": "0x1E050",
"EventName": "PM_CMPLU_STALL_TEND",
"BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting response from L2",
"PublicDescription": ""
},
{,
"EventCode": "0x1E15E",
"EventName": "PM_MRK_L2_TM_REQ_ABORT",
"BriefDescription": "TM abort",
"PublicDescription": ""
},
{,
"EventCode": "0x1F054",
"EventName": "PM_TLB_HIT",
"BriefDescription": "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT",
"PublicDescription": ""
},
{,
"EventCode": "0x1006A",
"EventName": "PM_NTC_ISSUE_HELD_DARQ_FULL",
"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it",
"PublicDescription": ""
"EventCode": "0x25044",
"EventName": "PM_IPTEG_FROM_L31_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request"
},
{,
"EventCode": "0x101E8",
"EventName": "PM_THRESH_EXC_256",
"BriefDescription": "Threshold counter exceed a count of 256",
"PublicDescription": ""
},
{,
"EventCode": "0x101EC",
"EventName": "PM_THRESH_MET",
"BriefDescription": "threshold exceeded",
"PublicDescription": ""
},
{,
"EventCode": "0x100F2",
"EventName": "PM_1PLUS_PPC_CMPL",
"BriefDescription": "1 or more ppc insts finished",
"PublicDescription": ""
},
{,
"EventCode": "0x20114",
"EventName": "PM_MRK_L2_RC_DISP",
"BriefDescription": "Marked Instruction RC dispatched in L2",
"PublicDescription": ""
},
{,
"EventCode": "0x2C010",
"EventName": "PM_CMPLU_STALL_LSU",
"BriefDescription": "Completion stall by LSU instruction",
"PublicDescription": ""
},
{,
"EventCode": "0x2C014",
"EventName": "PM_CMPLU_STALL_STORE_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish",
"PublicDescription": ""
},
{,
"EventCode": "0x2C01E",
"EventName": "PM_CMPLU_STALL_SYNC_PMU_INT",
"BriefDescription": "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt",
"PublicDescription": ""
},
{,
"EventCode": "0x2D01C",
"EventName": "PM_CMPLU_STALL_STCX",
"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from L2",
"PublicDescription": ""
},
{,
"EventCode": "0x2E01A",
"EventName": "PM_CMPLU_STALL_LSU_FLUSH_NEXT",
"BriefDescription": "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete",
"PublicDescription": ""
},
{,
"EventCode": "0x2C124",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2C042",
"EventName": "PM_DATA_FROM_L3_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x2D14C",
"EventName": "PM_MRK_DATA_FROM_L3.1_ECO_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x25042",
"EventName": "PM_IPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x25044",
"EventName": "PM_IPTEG_FROM_L3.1_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2015E",
"EventName": "PM_MRK_FAB_RSP_RWITM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty",
"PublicDescription": ""
},
{,
"EventCode": "0x24050",
"EventName": "PM_IOPS_CMPL",
"BriefDescription": "Internal Operations completed",
"PublicDescription": ""
},
{,
"EventCode": "0x24154",
"EventName": "PM_THRESH_ACC",
"BriefDescription": "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs.",
"PublicDescription": ""
},
{,
"EventCode": "0x2F152",
"EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC",
"BriefDescription": "cycles L2 RC took for a dclaim",
"PublicDescription": ""
},
{,
"EventCode": "0x200FA",
"EventName": "PM_BR_TAKEN_CMPL",
"BriefDescription": "New event for Branch Taken",
"PublicDescription": ""
},
{,
"EventCode": "0x30014",
"EventName": "PM_CMPLU_STALL_STORE_FIN_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe",
"PublicDescription": ""
},
{,
"EventCode": "0x3001C",
"EventName": "PM_LSU_REJECT_LMQ_FULL",
"BriefDescription": "LSU Reject due to LMQ full (up to 4 per cycles)",
"PublicDescription": ""
},
{,
"EventCode": "0x30026",
"EventName": "PM_CMPLU_STALL_STORE_DATA",
"BriefDescription": "Finish stall because the next to finish instruction was a store waiting on data",
"PublicDescription": ""
},
{,
"EventCode": "0x3012A",
"EventName": "PM_MRK_L2_RC_DONE",
"BriefDescription": "Marked RC done",
"PublicDescription": ""
},
{,
"EventCode": "0x35044",
"EventName": "PM_IPTEG_FROM_L3.1_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3E04A",
"EventName": "PM_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x30154",
"EventName": "PM_MRK_FAB_RSP_DCLAIM",
"BriefDescription": "Marked store had to do a dclaim",
"PublicDescription": ""
},
{,
"EventCode": "0x3015E",
"EventName": "PM_MRK_FAB_RSP_CLAIM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty",
"PublicDescription": ""
},
{,
"EventCode": "0x3C056",
"EventName": "PM_DTLB_MISS_64K",
"BriefDescription": "Data TLB Miss page size 64K",
"PublicDescription": ""
},
{,
"EventCode": "0x34050",
"EventName": "PM_INST_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch",
"PublicDescription": ""
},
{,
"EventCode": "0x34052",
"EventName": "PM_INST_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch",
"PublicDescription": ""
},
{,
"EventCode": "0x34056",
"EventName": "PM_CMPLU_STALL_LSU_MFSPR",
"BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned",
"PublicDescription": ""
},
{,
"EventCode": "0x3515A",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x3515C",
"EventName": "PM_MRK_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x3E15C",
"EventName": "PM_MRK_L2_TM_ST_ABORT_SISTER",
"BriefDescription": "TM marked store abort for this thread",
"PublicDescription": ""
},
{,
"EventCode": "0x30060",
"EventName": "PM_TM_TRANS_RUN_INST",
"BriefDescription": "Run instructions completed in transactional state (gated by the run latch)",
"PublicDescription": ""
},
{,
"EventCode": "0x301E6",
"EventName": "PM_MRK_DERAT_MISS",
"BriefDescription": "Erat Miss (TLB Access) All page sizes",
"PublicDescription": ""
},
{,
"EventCode": "0x301EA",
"EventName": "PM_THRESH_EXC_1024",
"BriefDescription": "Threshold counter exceeded a value of 1024",
"PublicDescription": ""
},
{,
"EventCode": "0x300FA",
"EventName": "PM_INST_FROM_L3MISS",
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet",
"PublicDescription": ""
},
{,
"EventCode": "0x40116",
"EventName": "PM_MRK_LARX_FIN",
"BriefDescription": "Larx finished",
"PublicDescription": ""
},
{,
"EventCode": "0x4C010",
"EventName": "PM_CMPLU_STALL_STORE_PIPE_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration",
"PublicDescription": ""
},
{,
"EventCode": "0x4C01C",
"EventName": "PM_CMPLU_STALL_ST_FWD",
"BriefDescription": "Completion stall due to store forward",
"PublicDescription": ""
},
{,
"EventCode": "0x4E012",
"EventName": "PM_CMPLU_STALL_MTFPSCR",
"BriefDescription": "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)",
"PublicDescription": ""
},
{,
"EventCode": "0x4E016",
"EventName": "PM_CMPLU_STALL_LSAQ_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch",
"PublicDescription": ""
},
{,
"EventCode": "0x4C12A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4C044",
"EventName": "PM_DATA_FROM_L3.1_ECO_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x45044",
"EventName": "PM_IPTEG_FROM_L3.1_ECO_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x45048",
"EventName": "PM_IPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
"PublicDescription": ""
"BriefDescription": "Threshold counter exceed a count of 256"
},
{,
"EventCode": "0x4504E",
"EventName": "PM_IPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request",
"PublicDescription": ""
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request"
},
{,
"EventCode": "0x4E042",
"EventName": "PM_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x1006A",
"EventName": "PM_NTC_ISSUE_HELD_DARQ_FULL",
"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it"
},
{,
"EventCode": "0x4015E",
"EventName": "PM_MRK_FAB_RSP_RD_RTY",
"BriefDescription": "Sampled L2 reads retry count",
"PublicDescription": ""
"EventCode": "0x4E016",
"EventName": "PM_CMPLU_STALL_LSAQ_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch"
},
{,
"EventCode": "0x4C056",
"EventName": "PM_DTLB_MISS_16M",
"BriefDescription": "Data TLB Miss page size 16M",
"PublicDescription": ""
"EventCode": "0x1001A",
"EventName": "PM_LSU_SRQ_FULL_CYC",
"BriefDescription": "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource"
},
{,
"EventCode": "0x1E15E",
"EventName": "PM_MRK_L2_TM_REQ_ABORT",
"BriefDescription": "TM abort"
},
{,
"EventCode": "0x34052",
"EventName": "PM_INST_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch"
},
{,
"EventCode": "0x20114",
"EventName": "PM_MRK_L2_RC_DISP",
"BriefDescription": "Marked Instruction RC dispatched in L2"
},
{,
"EventCode": "0x4C044",
"EventName": "PM_DATA_FROM_L31_ECO_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load"
},
{,
"EventCode": "0x1C044",
"EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load"
},
{,
"EventCode": "0x44050",
"EventName": "PM_INST_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch",
"PublicDescription": ""
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch"
},
{,
"EventCode": "0x44052",
"EventName": "PM_INST_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch",
"PublicDescription": ""
"EventCode": "0x30154",
"EventName": "PM_MRK_FAB_RSP_DCLAIM",
"BriefDescription": "Marked store had to do a dclaim"
},
{,
"EventCode": "0x30014",
"EventName": "PM_CMPLU_STALL_STORE_FIN_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe"
},
{,
"EventCode": "0x3E054",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
},
{,
"EventCode": "0x400F0",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
},
{,
"EventCode": "0x2E01A",
"EventName": "PM_CMPLU_STALL_LSU_FLUSH_NEXT",
"BriefDescription": "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete"
},
{,
"EventCode": "0x2D01C",
"EventName": "PM_CMPLU_STALL_STCX",
"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from L2"
},
{,
"EventCode": "0x2C010",
"EventName": "PM_CMPLU_STALL_LSU",
"BriefDescription": "Completion stall by LSU instruction"
},
{,
"EventCode": "0x2C042",
"EventName": "PM_DATA_FROM_L3_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load"
},
{,
"EventCode": "0x4E012",
"EventName": "PM_CMPLU_STALL_MTFPSCR",
"BriefDescription": "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)"
},
{,
"EventCode": "0x100F2",
"EventName": "PM_1PLUS_PPC_CMPL",
"BriefDescription": "1 or more ppc insts finished"
},
{,
"EventCode": "0x3001C",
"EventName": "PM_LSU_REJECT_LMQ_FULL",
"BriefDescription": "LSU Reject due to LMQ full (up to 4 per cycles)"
},
{,
"EventCode": "0x15046",
"EventName": "PM_IPTEG_FROM_L31_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request"
},
{,
"EventCode": "0x1015E",
"EventName": "PM_MRK_FAB_RSP_RD_T_INTV",
"BriefDescription": "Sampled Read got a T intervention"
},
{,
"EventCode": "0x101EC",
"EventName": "PM_THRESH_MET",
"BriefDescription": "threshold exceeded"
},
{,
"EventCode": "0x10020",
"EventName": "PM_PMC4_REWIND",
"BriefDescription": "PMC4 Rewind Event"
},
{,
"EventCode": "0x301EA",
"EventName": "PM_THRESH_EXC_1024",
"BriefDescription": "Threshold counter exceeded a value of 1024"
},
{,
"EventCode": "0x34056",
"EventName": "PM_CMPLU_STALL_LSU_MFSPR",
"BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned"
},
{,
"EventCode": "0x44056",
"EventName": "PM_VECTOR_ST_CMPL",
"BriefDescription": "Number of vector store instructions completed",
"PublicDescription": ""
"BriefDescription": "Number of vector store instructions completed"
},
{,
"EventCode": "0x2C124",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load"
},
{,
"EventCode": "0x4C12A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
{,
"EventCode": "0x3C056",
"EventName": "PM_DTLB_MISS_64K",
"BriefDescription": "Data TLB Miss page size 64K"
},
{,
"EventCode": "0x30060",
"EventName": "PM_TM_TRANS_RUN_INST",
"BriefDescription": "Run instructions completed in transactional state (gated by the run latch)"
},
{,
"EventCode": "0x2C014",
"EventName": "PM_CMPLU_STALL_STORE_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish"
},
{,
"EventCode": "0x3515A",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load"
},
{,
"EventCode": "0x34050",
"EventName": "PM_INST_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch"
},
{,
"EventCode": "0x3015E",
"EventName": "PM_MRK_FAB_RSP_CLAIM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty"
},
{,
"EventCode": "0x0",
"EventName": "PM_SUSPENDED",
"BriefDescription": "Counter OFF"
},
{,
"EventCode": "0x10010",
"EventName": "PM_PMC4_OVERFLOW",
"BriefDescription": "Overflow from counter 4"
},
{,
"EventCode": "0x3E04A",
"EventName": "PM_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2F152",
"EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC",
"BriefDescription": "cycles L2 RC took for a dclaim"
},
{,
"EventCode": "0x10004",
"EventName": "PM_CMPLU_STALL_LRQ_OTHER",
"BriefDescription": "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others"
},
{,
"EventCode": "0x4F150",
"EventName": "PM_MRK_FAB_RSP_RWITM_CYC",
"BriefDescription": "cycles L2 RC took for a rwitm",
"PublicDescription": ""
"BriefDescription": "cycles L2 RC took for a rwitm"
},
{,
"EventCode": "0x4E042",
"EventName": "PM_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x1F054",
"EventName": "PM_TLB_HIT",
"BriefDescription": "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT"
},
{,
"EventCode": "0x2C01E",
"EventName": "PM_CMPLU_STALL_SYNC_PMU_INT",
"BriefDescription": "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt"
},
{,
"EventCode": "0x24050",
"EventName": "PM_IOPS_CMPL",
"BriefDescription": "Internal Operations completed"
},
{,
"EventCode": "0x1515C",
"EventName": "PM_SYNC_MRK_BR_MPRED",
"BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt"
},
{,
"EventCode": "0x300FA",
"EventName": "PM_INST_FROM_L3MISS",
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet"
},
{,
"EventCode": "0x15044",
"EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request"
},
{,
"EventCode": "0x15152",
"EventName": "PM_SYNC_MRK_BR_LINK",
"BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt"
},
{,
"EventCode": "0x1E050",
"EventName": "PM_CMPLU_STALL_TEND",
"BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting response from L2"
},
{,
"EventCode": "0x1013E",
"EventName": "PM_MRK_LD_MISS_EXPOSED_CYC",
"BriefDescription": "Marked Load exposed Miss (use edge detect to count #)"
},
{,
"EventCode": "0x25042",
"EventName": "PM_IPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request"
},
{,
"EventCode": "0x14054",
"EventName": "PM_INST_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch"
},
{,
"EventCode": "0x4015E",
"EventName": "PM_MRK_FAB_RSP_RD_RTY",
"BriefDescription": "Sampled L2 reads retry count"
},
{,
"EventCode": "0x45048",
"EventName": "PM_IPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request"
},
{,
"EventCode": "0x44052",
"EventName": "PM_INST_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch"
},
{,
"EventCode": "0x30026",
"EventName": "PM_CMPLU_STALL_STORE_DATA",
"BriefDescription": "Finish stall because the next to finish instruction was a store waiting on data"
},
{,
"EventCode": "0x301E6",
"EventName": "PM_MRK_DERAT_MISS",
"BriefDescription": "Erat Miss (TLB Access) All page sizes"
},
{,
"EventCode": "0x24154",
"EventName": "PM_THRESH_ACC",
"BriefDescription": "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs."
},
{,
"EventCode": "0x2015E",
"EventName": "PM_MRK_FAB_RSP_RWITM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty"
},
{,
"EventCode": "0x200FA",
"EventName": "PM_BR_TAKEN_CMPL",
"BriefDescription": "New event for Branch Taken"
},
{,
"EventCode": "0x35044",
"EventName": "PM_IPTEG_FROM_L31_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request"
},
{,
"EventCode": "0x4C010",
"EventName": "PM_CMPLU_STALL_STORE_PIPE_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration"
},
{,
"EventCode": "0x4C01C",
"EventName": "PM_CMPLU_STALL_ST_FWD",
"BriefDescription": "Completion stall due to store forward"
},
{,
"EventCode": "0x3515C",
"EventName": "PM_MRK_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
},
{,
"EventCode": "0x2D14C",
"EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load"
},
{,
"EventCode": "0x40116",
"EventName": "PM_MRK_LARX_FIN",
"BriefDescription": "Larx finished"
},
{,
"EventCode": "0x4C056",
"EventName": "PM_DTLB_MISS_16M",
"BriefDescription": "Data TLB Miss page size 16M"
},
{,
"EventCode": "0x1003A",
"EventName": "PM_CMPLU_STALL_LSU_FIN",
"BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish"
},
{,
"EventCode": "0x3012A",
"EventName": "PM_MRK_L2_RC_DONE",
"BriefDescription": "Marked RC done"
},
{,
"EventCode": "0x45044",
"EventName": "PM_IPTEG_FROM_L31_ECO_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request"
}
]
]

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tools/perf/pmu-events/arch/powerpc/power9/marked.json
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tools/perf/pmu-events/arch/powerpc/power9/memory.json
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@ -1,158 +1,132 @@
[
{,
"EventCode": "0x10008",
"EventName": "PM_RUN_SPURR",
"BriefDescription": "Run SPURR",
"PublicDescription": ""
},
{,
"EventCode": "0x1000A",
"EventName": "PM_PMC3_REWIND",
"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change.",
"PublicDescription": ""
},
{,
"EventCode": "0x1C040",
"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x1C050",
"EventName": "PM_DATA_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x1D15E",
"EventName": "PM_MRK_RUN_CYC",
"BriefDescription": "Run cycles in which a marked instruction is in the pipeline",
"PublicDescription": ""
},
{,
"EventCode": "0x15158",
"EventName": "PM_SYNC_MRK_L2HIT",
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt",
"PublicDescription": ""
"EventCode": "0x3006E",
"EventName": "PM_NEST_REF_CLK",
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles"
},
{,
"EventCode": "0x20010",
"EventName": "PM_PMC1_OVERFLOW",
"BriefDescription": "Overflow from counter 1",
"PublicDescription": ""
},
{,
"EventCode": "0x2C040",
"EventName": "PM_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
"PublicDescription": ""
"BriefDescription": "Overflow from counter 1"
},
{,
"EventCode": "0x2005A",
"EventName": "PM_DARQ1_7_9_ENTRIES",
"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use",
"PublicDescription": ""
},
{,
"EventCode": "0x2C05C",
"EventName": "PM_INST_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)",
"PublicDescription": ""
},
{,
"EventCode": "0x2D156",
"EventName": "PM_MRK_DTLB_MISS_4K",
"BriefDescription": "Marked Data TLB Miss page size 4k",
"PublicDescription": ""
},
{,
"EventCode": "0x2E05A",
"EventName": "PM_LRQ_REJECT",
"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects",
"PublicDescription": ""
},
{,
"EventCode": "0x2E05C",
"EventName": "PM_LSU_REJECT_ERAT_MISS",
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)",
"PublicDescription": ""
},
{,
"EventCode": "0x200F6",
"EventName": "PM_LSU_DERAT_MISS",
"BriefDescription": "DERAT Reloaded due to a DERAT miss",
"PublicDescription": ""
"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use"
},
{,
"EventCode": "0x3C048",
"EventName": "PM_DATA_FROM_DL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
"PublicDescription": ""
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
},
{,
"EventCode": "0x3404A",
"EventName": "PM_INST_FROM_RMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x10008",
"EventName": "PM_RUN_SPURR",
"BriefDescription": "Run SPURR"
},
{,
"EventCode": "0x3C058",
"EventName": "PM_LARX_FIN",
"BriefDescription": "Larx finished",
"PublicDescription": ""
},
{,
"EventCode": "0x3E050",
"EventName": "PM_DARQ1_4_6_ENTRIES",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use",
"PublicDescription": ""
},
{,
"EventCode": "0x3006E",
"EventName": "PM_NEST_REF_CLK",
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles",
"PublicDescription": ""
},
{,
"EventCode": "0x301E2",
"EventName": "PM_MRK_ST_CMPL",
"BriefDescription": "Marked store completed and sent to nest",
"PublicDescription": ""
},
{,
"EventCode": "0x4D02C",
"EventName": "PM_PMC1_REWIND",
"BriefDescription": "",
"PublicDescription": ""
},
{,
"EventCode": "0x4003E",
"EventName": "PM_LD_CMPL",
"BriefDescription": "count of Loads completed",
"PublicDescription": ""
},
{,
"EventCode": "0x4C040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x4C042",
"EventName": "PM_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load",
"PublicDescription": ""
"EventCode": "0x200F6",
"EventName": "PM_LSU_DERAT_MISS",
"BriefDescription": "DERAT Reloaded due to a DERAT miss"
},
{,
"EventCode": "0x4C048",
"EventName": "PM_DATA_FROM_DL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
"PublicDescription": ""
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
},
{,
"EventCode": "0x1D15E",
"EventName": "PM_MRK_RUN_CYC",
"BriefDescription": "Run cycles in which a marked instruction is in the pipeline"
},
{,
"EventCode": "0x4003E",
"EventName": "PM_LD_CMPL",
"BriefDescription": "count of Loads completed"
},
{,
"EventCode": "0x2D156",
"EventName": "PM_MRK_DTLB_MISS_4K",
"BriefDescription": "Marked Data TLB Miss page size 4k"
},
{,
"EventCode": "0x4C042",
"EventName": "PM_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load"
},
{,
"EventCode": "0x4D02C",
"EventName": "PM_PMC1_REWIND",
"BriefDescription": ""
},
{,
"EventCode": "0x15158",
"EventName": "PM_SYNC_MRK_L2HIT",
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt"
},
{,
"EventCode": "0x3404A",
"EventName": "PM_INST_FROM_RMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x301E2",
"EventName": "PM_MRK_ST_CMPL",
"BriefDescription": "Marked store completed and sent to nest"
},
{,
"EventCode": "0x1C050",
"EventName": "PM_DATA_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load"
},
{,
"EventCode": "0x4C040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load"
},
{,
"EventCode": "0x2E05C",
"EventName": "PM_LSU_REJECT_ERAT_MISS",
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)"
},
{,
"EventCode": "0x1000A",
"EventName": "PM_PMC3_REWIND",
"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change."
},
{,
"EventCode": "0x3C058",
"EventName": "PM_LARX_FIN",
"BriefDescription": "Larx finished"
},
{,
"EventCode": "0x1C040",
"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load"
},
{,
"EventCode": "0x2C040",
"EventName": "PM_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load"
},
{,
"EventCode": "0x2E05A",
"EventName": "PM_LRQ_REJECT",
"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects"
},
{,
"EventCode": "0x2C05C",
"EventName": "PM_INST_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)"
},
{,
"EventCode": "0x4D056",
"EventName": "PM_NON_FMA_FLOP_CMPL",
"BriefDescription": "Non FMA instruction completed",
"PublicDescription": ""
"BriefDescription": "Non FMA instruction completed"
},
{,
"EventCode": "0x3E050",
"EventName": "PM_DARQ1_4_6_ENTRIES",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use"
}
]

3246
tools/perf/pmu-events/arch/powerpc/power9/other.json
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tools/perf/pmu-events/arch/powerpc/power9/pipeline.json
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tools/perf/pmu-events/arch/powerpc/power9/pmc.json
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@ -1,146 +1,127 @@
[
{,
"EventCode": "0x0",
"EventName": "PM_SUSPENDED",
"BriefDescription": "Counter OFF",
"PublicDescription": ""
"EventCode": "0x20036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "Branches that are not strongly biased"
},
{,
"EventCode": "0x10026",
"EventName": "PM_TABLEWALK_CYC",
"BriefDescription": "Cycles when an instruction tablewalk is active",
"PublicDescription": ""
},
{,
"EventCode": "0x1E04C",
"EventName": "PM_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x1F14E",
"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x10060",
"EventName": "PM_TM_TRANS_RUN_CYC",
"BriefDescription": "run cycles in transactional state",
"PublicDescription": ""
},
{,
"EventCode": "0x2C012",
"EventName": "PM_CMPLU_STALL_DCACHE_MISS",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest",
"PublicDescription": ""
},
{,
"EventCode": "0x2E04C",
"EventName": "PM_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x2C056",
"EventName": "PM_DTLB_MISS_4K",
"BriefDescription": "Data TLB Miss page size 4k",
"PublicDescription": ""
},
{,
"EventCode": "0x3000C",
"EventName": "PM_FREQ_DOWN",
"BriefDescription": "Power Management: Below Threshold B",
"PublicDescription": ""
},
{,
"EventCode": "0x3D142",
"EventName": "PM_MRK_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x3F142",
"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x301E8",
"EventName": "PM_THRESH_EXC_64",
"BriefDescription": "Threshold counter exceeded a value of 64",
"PublicDescription": ""
},
{,
"EventCode": "0x40118",
"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
"BriefDescription": "Combined Intervention event",
"PublicDescription": ""
},
{,
"EventCode": "0x4C01E",
"EventName": "PM_CMPLU_STALL_CRYPTO",
"BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish",
"PublicDescription": ""
},
{,
"EventCode": "0x4D018",
"EventName": "PM_CMPLU_STALL_BRU",
"BriefDescription": "Completion stall due to a Branch Unit",
"PublicDescription": ""
},
{,
"EventCode": "0x4D128",
"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4E04E",
"EventName": "PM_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x4F142",
"EventName": "PM_MRK_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x4F148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x40050",
"EventName": "PM_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
"EventCode": "0x40036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "Branches that are not strongly biased"
},
{,
"EventCode": "0x40056",
"EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
"BriefDescription": "Local memory above threshold for LSU medium",
"PublicDescription": ""
"BriefDescription": "Local memory above threshold for LSU medium"
},
{,
"EventCode": "0x4D054",
"EventName": "PM_8FLOP_CMPL",
"BriefDescription": "8 FLOP instruction completed",
"PublicDescription": ""
"EventCode": "0x2C056",
"EventName": "PM_DTLB_MISS_4K",
"BriefDescription": "Data TLB Miss page size 4k"
},
{,
"EventCode": "0x45050",
"EventName": "PM_1FLOP_CMPL",
"BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed",
"PublicDescription": ""
"EventCode": "0x40118",
"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
"BriefDescription": "Combined Intervention event"
},
{,
"EventCode": "0x4F148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x301E8",
"EventName": "PM_THRESH_EXC_64",
"BriefDescription": "Threshold counter exceeded a value of 64"
},
{,
"EventCode": "0x4E04E",
"EventName": "PM_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x40050",
"EventName": "PM_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x1F14E",
"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x4D018",
"EventName": "PM_CMPLU_STALL_BRU",
"BriefDescription": "Completion stall due to a Branch Unit"
},
{,
"EventCode": "0x45052",
"EventName": "PM_4FLOP_CMPL",
"BriefDescription": "4 FLOP instruction completed",
"PublicDescription": ""
"BriefDescription": "4 FLOP instruction completed"
},
{,
"EventCode": "0x3D142",
"EventName": "PM_MRK_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load"
},
{,
"EventCode": "0x4C01E",
"EventName": "PM_CMPLU_STALL_CRYPTO",
"BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish"
},
{,
"EventCode": "0x3000C",
"EventName": "PM_FREQ_DOWN",
"BriefDescription": "Power Management: Below Threshold B"
},
{,
"EventCode": "0x4D128",
"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load"
},
{,
"EventCode": "0x4D054",
"EventName": "PM_8FLOP_CMPL",
"BriefDescription": "8 FLOP instruction completed"
},
{,
"EventCode": "0x10026",
"EventName": "PM_TABLEWALK_CYC",
"BriefDescription": "Cycles when an instruction tablewalk is active"
},
{,
"EventCode": "0x2C012",
"EventName": "PM_CMPLU_STALL_DCACHE_MISS",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest"
},
{,
"EventCode": "0x2E04C",
"EventName": "PM_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x3F142",
"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x4F142",
"EventName": "PM_MRK_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x10060",
"EventName": "PM_TM_TRANS_RUN_CYC",
"BriefDescription": "run cycles in transactional state"
},
{,
"EventCode": "0x1E04C",
"EventName": "PM_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x45050",
"EventName": "PM_1FLOP_CMPL",
"BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed"
}
]
]

468
tools/perf/pmu-events/arch/powerpc/power9/translation.json
View file

@ -1,272 +1,232 @@
[
{,
"EventCode": "0x10028",
"EventName": "PM_STALL_END_ICT_EMPTY",
"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this thread",
"PublicDescription": ""
},
{,
"EventCode": "0x1C04E",
"EventName": "PM_DATA_FROM_L2MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x14044",
"EventName": "PM_INST_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x1404E",
"EventName": "PM_INST_FROM_L2MISS",
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x1D142",
"EventName": "PM_MRK_DATA_FROM_L3.1_ECO_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x15048",
"EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1504A",
"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1E058",
"EventName": "PM_STCX_FAIL",
"BriefDescription": "stcx failed",
"PublicDescription": ""
},
{,
"EventCode": "0x1F15E",
"EventName": "PM_MRK_PROBE_NOP_CMPL",
"BriefDescription": "Marked probeNops completed",
"PublicDescription": ""
},
{,
"EventCode": "0x20112",
"EventName": "PM_MRK_NTF_FIN",
"BriefDescription": "Marked next to finish instruction finished",
"PublicDescription": ""
},
{,
"EventCode": "0x20016",
"EventName": "PM_ST_FIN",
"BriefDescription": "Store finish count. Includes speculative activity",
"PublicDescription": ""
},
{,
"EventCode": "0x20018",
"EventName": "PM_ST_FWD",
"BriefDescription": "Store forwards that finished",
"PublicDescription": ""
},
{,
"EventCode": "0x2011C",
"EventName": "PM_MRK_NTC_CYC",
"BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)",
"PublicDescription": ""
},
{,
"EventCode": "0x2E018",
"EventName": "PM_CMPLU_STALL_VFXLONG",
"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)",
"PublicDescription": ""
},
{,
"EventCode": "0x2E01C",
"EventName": "PM_CMPLU_STALL_TLBIE",
"BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2",
"PublicDescription": ""
},
{,
"EventCode": "0x2003E",
"EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
"BriefDescription": "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)",
"PublicDescription": ""
},
{,
"EventCode": "0x24042",
"EventName": "PM_INST_FROM_L3_MEPF",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x2D14A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x25046",
"EventName": "PM_IPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2504A",
"EventName": "PM_IPTEG_FROM_RL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2504C",
"EventName": "PM_IPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x201E6",
"EventName": "PM_THRESH_EXC_32",
"BriefDescription": "Threshold counter exceeded a value of 32",
"PublicDescription": ""
},
{,
"EventCode": "0x200F0",
"EventName": "PM_ST_CMPL",
"BriefDescription": "Stores completed from S2Q (2nd-level store queue).",
"PublicDescription": ""
},
{,
"EventCode": "0x200FE",
"EventName": "PM_DATA_FROM_L2MISS",
"BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
"PublicDescription": ""
"EventCode": "0x1E",
"EventName": "PM_CYC",
"BriefDescription": "Processor cycles"
},
{,
"EventCode": "0x30010",
"EventName": "PM_PMC2_OVERFLOW",
"BriefDescription": "Overflow from counter 2",
"PublicDescription": ""
"BriefDescription": "Overflow from counter 2"
},
{,
"EventCode": "0x3C046",
"EventName": "PM_DATA_FROM_L2.1_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x34042",
"EventName": "PM_INST_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x34046",
"EventName": "PM_INST_FROM_L2.1_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x3504A",
"EventName": "PM_IPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3E048",
"EventName": "PM_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x3E04C",
"EventName": "PM_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x3C05A",
"EventName": "PM_CMPLU_STALL_VDPLONG",
"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle",
"PublicDescription": ""
},
{,
"EventCode": "0x3C05C",
"EventName": "PM_CMPLU_STALL_VFXU",
"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
"PublicDescription": ""
},
{,
"EventCode": "0x30066",
"EventName": "PM_LSU_FIN",
"BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)",
"PublicDescription": ""
},
{,
"EventCode": "0x300F0",
"EventName": "PM_ST_MISS_L1",
"BriefDescription": "Store Missed L1",
"PublicDescription": ""
},
{,
"EventCode": "0x4D010",
"EventName": "PM_PMC1_SAVED",
"BriefDescription": "PMC1 Rewind Value saved",
"PublicDescription": ""
},
{,
"EventCode": "0x40132",
"EventName": "PM_MRK_LSU_FIN",
"BriefDescription": "lsu marked instr PPC finish",
"PublicDescription": ""
},
{,
"EventCode": "0x4C046",
"EventName": "PM_DATA_FROM_L2.1_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x44042",
"EventName": "PM_INST_FROM_L3",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x4504A",
"EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4E048",
"EventName": "PM_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x4E04C",
"EventName": "PM_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
},
{,
"EventCode": "0x4405C",
"EventName": "PM_CMPLU_STALL_VDP",
"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector",
"PublicDescription": ""
"EventName": "PM_DATA_FROM_L21_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load"
},
{,
"EventCode": "0x4D05C",
"EventName": "PM_DP_QP_FLOP_CMPL",
"BriefDescription": "Double-Precion or Quad-Precision instruction completed",
"PublicDescription": ""
"BriefDescription": "Double-Precion or Quad-Precision instruction completed"
},
{,
"EventCode": "0x4E04C",
"EventName": "PM_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x20016",
"EventName": "PM_ST_FIN",
"BriefDescription": "Store finish count. Includes speculative activity"
},
{,
"EventCode": "0x44042",
"EventName": "PM_INST_FROM_L3",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x1504A",
"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
},
{,
"EventCode": "0x40132",
"EventName": "PM_MRK_LSU_FIN",
"BriefDescription": "lsu marked instr PPC finish"
},
{,
"EventCode": "0x3C05C",
"EventName": "PM_CMPLU_STALL_VFXU",
"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
},
{,
"EventCode": "0x30066",
"EventName": "PM_LSU_FIN",
"BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
},
{,
"EventCode": "0x2011C",
"EventName": "PM_MRK_NTC_CYC",
"BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)"
},
{,
"EventCode": "0x3E048",
"EventName": "PM_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2E018",
"EventName": "PM_CMPLU_STALL_VFXLONG",
"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)"
},
{,
"EventCode": "0x1C04E",
"EventName": "PM_DATA_FROM_L2MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load"
},
{,
"EventCode": "0x15048",
"EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
},
{,
"EventCode": "0x34046",
"EventName": "PM_INST_FROM_L21_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x1E058",
"EventName": "PM_STCX_FAIL",
"BriefDescription": "stcx failed"
},
{,
"EventCode": "0x20112",
"EventName": "PM_MRK_NTF_FIN",
"BriefDescription": "Marked next to finish instruction finished"
},
{,
"EventCode": "0x300F0",
"EventName": "PM_ST_MISS_L1",
"BriefDescription": "Store Missed L1"
},
{,
"EventCode": "0x4C046",
"EventName": "PM_DATA_FROM_L21_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load"
},
{,
"EventCode": "0x2504A",
"EventName": "PM_IPTEG_FROM_RL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
},
{,
"EventCode": "0x2003E",
"EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
"BriefDescription": "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)"
},
{,
"EventCode": "0x201E6",
"EventName": "PM_THRESH_EXC_32",
"BriefDescription": "Threshold counter exceeded a value of 32"
},
{,
"EventCode": "0x4405C",
"EventName": "PM_CMPLU_STALL_VDP",
"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector"
},
{,
"EventCode": "0x4D010",
"EventName": "PM_PMC1_SAVED",
"BriefDescription": "PMC1 Rewind Value saved"
},
{,
"EventCode": "0x200FE",
"EventName": "PM_DATA_FROM_L2MISS",
"BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
},
{,
"EventCode": "0x2D14A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
{,
"EventCode": "0x10028",
"EventName": "PM_STALL_END_ICT_EMPTY",
"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this thread"
},
{,
"EventCode": "0x2504C",
"EventName": "PM_IPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request"
},
{,
"EventCode": "0x4504A",
"EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request"
},
{,
"EventCode": "0x1404E",
"EventName": "PM_INST_FROM_L2MISS",
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x34042",
"EventName": "PM_INST_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x4E048",
"EventName": "PM_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x200F0",
"EventName": "PM_ST_CMPL",
"BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
},
{,
"EventCode": "0x4E05C",
"EventName": "PM_LSU_REJECT_LHS",
"BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)",
"PublicDescription": ""
"BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)"
},
{,
"EventCode": "0x14044",
"EventName": "PM_INST_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x3E04C",
"EventName": "PM_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x1F15E",
"EventName": "PM_MRK_PROBE_NOP_CMPL",
"BriefDescription": "Marked probeNops completed"
},
{,
"EventCode": "0x20018",
"EventName": "PM_ST_FWD",
"BriefDescription": "Store forwards that finished"
},
{,
"EventCode": "0x1D142",
"EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load"
},
{,
"EventCode": "0x24042",
"EventName": "PM_INST_FROM_L3_MEPF",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x25046",
"EventName": "PM_IPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
},
{,
"EventCode": "0x3504A",
"EventName": "PM_IPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request"
},
{,
"EventCode": "0x3C05A",
"EventName": "PM_CMPLU_STALL_VDPLONG",
"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle"
},
{,
"EventCode": "0x2E01C",
"EventName": "PM_CMPLU_STALL_TLBIE",
"BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2"
}
]
]

1
tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py
View file

@ -57,6 +57,7 @@ try:
'ia64' : audit.MACH_IA64,
'ppc' : audit.MACH_PPC,
'ppc64' : audit.MACH_PPC64,
'ppc64le' : audit.MACH_PPC64LE,
's390' : audit.MACH_S390,
's390x' : audit.MACH_S390X,
'i386' : audit.MACH_X86,

2
tools/perf/tests/attr.c
View file

@ -169,7 +169,7 @@ static int run_dir(const char *d, const char *perf)
return system(cmd);
}
int test__attr(int subtest __maybe_unused)
int test__attr(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct stat st;
char path_perf[PATH_MAX];

2
tools/perf/tests/backward-ring-buffer.c
View file

@ -75,7 +75,7 @@ static int do_test(struct perf_evlist *evlist, int mmap_pages,
}
int test__backward_ring_buffer(int subtest __maybe_unused)
int test__backward_ring_buffer(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int ret = TEST_SKIP, err, sample_count = 0, comm_count = 0;
char pid[16], sbuf[STRERR_BUFSIZE];

2
tools/perf/tests/bitmap.c
View file

@ -40,7 +40,7 @@ static int test_bitmap(const char *str)
return ret;
}
int test__bitmap_print(int subtest __maybe_unused)
int test__bitmap_print(struct test *test __maybe_unused, int subtest __maybe_unused)
{
TEST_ASSERT_VAL("failed to convert map", test_bitmap("1"));
TEST_ASSERT_VAL("failed to convert map", test_bitmap("1,5"));

2
tools/perf/tests/bp_signal.c
View file

@ -164,7 +164,7 @@ static long long bp_count(int fd)
return count;
}
int test__bp_signal(int subtest __maybe_unused)
int test__bp_signal(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct sigaction sa;
long long count1, count2, count3;

2
tools/perf/tests/bp_signal_overflow.c
View file

@ -57,7 +57,7 @@ static long long bp_count(int fd)
#define EXECUTIONS 10000
#define THRESHOLD 100
int test__bp_signal_overflow(int subtest __maybe_unused)
int test__bp_signal_overflow(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct perf_event_attr pe;
struct sigaction sa;

4
tools/perf/tests/bpf.c
View file

@ -321,7 +321,7 @@ static int check_env(void)
return 0;
}
int test__bpf(int i)
int test__bpf(struct test *test __maybe_unused, int i)
{
int err;
@ -351,7 +351,7 @@ const char *test__bpf_subtest_get_desc(int i __maybe_unused)
return NULL;
}
int test__bpf(int i __maybe_unused)
int test__bpf(struct test *test __maybe_unused, int i __maybe_unused)
{
pr_debug("Skip BPF test because BPF support is not compiled\n");
return TEST_SKIP;

184
tools/perf/tests/builtin-test.c
View file

@ -6,7 +6,10 @@
#include <errno.h>
#include <unistd.h>
#include <string.h>
#include <sys/types.h>
#include <dirent.h>
#include <sys/wait.h>
#include <sys/stat.h>
#include "builtin.h"
#include "hist.h"
#include "intlist.h"
@ -14,8 +17,10 @@
#include "debug.h"
#include "color.h"
#include <subcmd/parse-options.h>
#include "string2.h"
#include "symbol.h"
#include <linux/kernel.h>
#include <subcmd/exec-cmd.h>
static bool dont_fork;
@ -179,7 +184,7 @@ static struct test generic_tests[] = {
},
{
.desc = "Session topology",
.func = test_session_topology,
.func = test__session_topology,
},
{
.desc = "BPF filter",
@ -325,7 +330,7 @@ static int run_test(struct test *test, int subtest)
}
}
err = test->func(subtest);
err = test->func(test, subtest);
if (!dont_fork)
exit(err);
}
@ -383,12 +388,143 @@ static int test_and_print(struct test *t, bool force_skip, int subtest)
return err;
}
static const char *shell_test__description(char *description, size_t size,
const char *path, const char *name)
{
FILE *fp;
char filename[PATH_MAX];
path__join(filename, sizeof(filename), path, name);
fp = fopen(filename, "r");
if (!fp)
return NULL;
description = fgets(description, size, fp);
fclose(fp);
return description ? trim(description + 1) : NULL;
}
#define for_each_shell_test(dir, ent) \
while ((ent = readdir(dir)) != NULL) \
if (ent->d_type == DT_REG && ent->d_name[0] != '.')
static const char *shell_tests__dir(char *path, size_t size)
{
const char *devel_dirs[] = { "./tools/perf/tests", "./tests", };
char *exec_path;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(devel_dirs); ++i) {
struct stat st;
if (!lstat(devel_dirs[i], &st)) {
scnprintf(path, size, "%s/shell", devel_dirs[i]);
if (!lstat(devel_dirs[i], &st))
return path;
}
}
/* Then installed path. */
exec_path = get_argv_exec_path();
scnprintf(path, size, "%s/tests/shell", exec_path);
free(exec_path);
return path;
}
static int shell_tests__max_desc_width(void)
{
DIR *dir;
struct dirent *ent;
char path_dir[PATH_MAX];
const char *path = shell_tests__dir(path_dir, sizeof(path_dir));
int width = 0;
if (path == NULL)
return -1;
dir = opendir(path);
if (!dir)
return -1;
for_each_shell_test(dir, ent) {
char bf[256];
const char *desc = shell_test__description(bf, sizeof(bf), path, ent->d_name);
if (desc) {
int len = strlen(desc);
if (width < len)
width = len;
}
}
closedir(dir);
return width;
}
struct shell_test {
const char *dir;
const char *file;
};
static int shell_test__run(struct test *test, int subdir __maybe_unused)
{
int err;
char script[PATH_MAX];
struct shell_test *st = test->priv;
path__join(script, sizeof(script), st->dir, st->file);
err = system(script);
if (!err)
return TEST_OK;
return WEXITSTATUS(err) == 2 ? TEST_SKIP : TEST_FAIL;
}
static int run_shell_tests(int argc, const char *argv[], int i, int width)
{
DIR *dir;
struct dirent *ent;
char path_dir[PATH_MAX];
struct shell_test st = {
.dir = shell_tests__dir(path_dir, sizeof(path_dir)),
};
if (st.dir == NULL)
return -1;
dir = opendir(st.dir);
if (!dir)
return -1;
for_each_shell_test(dir, ent) {
int curr = i++;
char desc[256];
struct test test = {
.desc = shell_test__description(desc, sizeof(desc), st.dir, ent->d_name),
.func = shell_test__run,
.priv = &st,
};
if (!perf_test__matches(&test, curr, argc, argv))
continue;
st.file = ent->d_name;
pr_info("%2d: %-*s:", i, width, test.desc);
test_and_print(&test, false, -1);
}
closedir(dir);
return 0;
}
static int __cmd_test(int argc, const char *argv[], struct intlist *skiplist)
{
struct test *t;
unsigned int j;
int i = 0;
int width = 0;
int width = shell_tests__max_desc_width();
for_each_test(j, t) {
int len = strlen(t->desc);
@ -455,6 +591,37 @@ static int __cmd_test(int argc, const char *argv[], struct intlist *skiplist)
}
}
return run_shell_tests(argc, argv, i, width);
}
static int perf_test__list_shell(int argc, const char **argv, int i)
{
DIR *dir;
struct dirent *ent;
char path_dir[PATH_MAX];
const char *path = shell_tests__dir(path_dir, sizeof(path_dir));
if (path == NULL)
return -1;
dir = opendir(path);
if (!dir)
return -1;
for_each_shell_test(dir, ent) {
int curr = i++;
char bf[256];
struct test t = {
.desc = shell_test__description(bf, sizeof(bf), path, ent->d_name),
};
if (!perf_test__matches(&t, curr, argc, argv))
continue;
pr_info("%2d: %s\n", i, t.desc);
}
closedir(dir);
return 0;
}
@ -465,12 +632,17 @@ static int perf_test__list(int argc, const char **argv)
int i = 0;
for_each_test(j, t) {
if (argc > 1 && !strstr(t->desc, argv[1]))
int curr = i++;
if (!perf_test__matches(t, curr, argc, argv) ||
(t->is_supported && !t->is_supported()))
continue;
pr_info("%2d: %s\n", ++i, t->desc);
pr_info("%2d: %s\n", i, t->desc);
}
perf_test__list_shell(argc, argv, i);
return 0;
}
@ -498,7 +670,7 @@ int cmd_test(int argc, const char **argv)
argc = parse_options_subcommand(argc, argv, test_options, test_subcommands, test_usage, 0);
if (argc >= 1 && !strcmp(argv[0], "list"))
return perf_test__list(argc, argv);
return perf_test__list(argc - 1, argv + 1);
symbol_conf.priv_size = sizeof(int);
symbol_conf.sort_by_name = true;

4
tools/perf/tests/clang.c
View file

@ -33,12 +33,12 @@ const char *test__clang_subtest_get_desc(int i)
}
#ifndef HAVE_LIBCLANGLLVM_SUPPORT
int test__clang(int i __maybe_unused)
int test__clang(struct test *test __maybe_unused, int i __maybe_unused)
{
return TEST_SKIP;
}
#else
int test__clang(int i)
int test__clang(struct test *test __maybe_unused, int i)
{
if (i < 0 || i >= (int)ARRAY_SIZE(clang_testcase_table))
return TEST_FAIL;

2
tools/perf/tests/code-reading.c
View file

@ -673,7 +673,7 @@ out_err:
return err;
}
int test__code_reading(int subtest __maybe_unused)
int test__code_reading(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int ret;

4
tools/perf/tests/cpumap.c
View file

@ -72,7 +72,7 @@ static int process_event_cpus(struct perf_tool *tool __maybe_unused,
}
int test__cpu_map_synthesize(int subtest __maybe_unused)
int test__cpu_map_synthesize(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct cpu_map *cpus;
@ -106,7 +106,7 @@ static int cpu_map_print(const char *str)
return !strcmp(buf, str);
}
int test__cpu_map_print(int subtest __maybe_unused)
int test__cpu_map_print(struct test *test __maybe_unused, int subtest __maybe_unused)
{
TEST_ASSERT_VAL("failed to convert map", cpu_map_print("1"));
TEST_ASSERT_VAL("failed to convert map", cpu_map_print("1,5"));

6
tools/perf/tests/dso-data.c
View file

@ -112,7 +112,7 @@ static int dso__data_fd(struct dso *dso, struct machine *machine)
return fd;
}
int test__dso_data(int subtest __maybe_unused)
int test__dso_data(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct machine machine;
struct dso *dso;
@ -247,7 +247,7 @@ static int set_fd_limit(int n)
return setrlimit(RLIMIT_NOFILE, &rlim);
}
int test__dso_data_cache(int subtest __maybe_unused)
int test__dso_data_cache(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct machine machine;
long nr_end, nr = open_files_cnt();
@ -307,7 +307,7 @@ int test__dso_data_cache(int subtest __maybe_unused)
return 0;
}
int test__dso_data_reopen(int subtest __maybe_unused)
int test__dso_data_reopen(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct machine machine;
long nr_end, nr = open_files_cnt();

2
tools/perf/tests/dwarf-unwind.c
View file

@ -154,7 +154,7 @@ static noinline int krava_1(struct thread *thread)
return krava_2(thread);
}
int test__dwarf_unwind(int subtest __maybe_unused)
int test__dwarf_unwind(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct machine *machine;
struct thread *thread;

2
tools/perf/tests/event-times.c
View file

@ -213,7 +213,7 @@ out_err:
* and checks that enabled and running times
* match.
*/
int test__event_times(int subtest __maybe_unused)
int test__event_times(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err, ret = 0;

2
tools/perf/tests/event_update.c
View file

@ -76,7 +76,7 @@ static int process_event_cpus(struct perf_tool *tool __maybe_unused,
return 0;
}
int test__event_update(int subtest __maybe_unused)
int test__event_update(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct perf_evlist *evlist;
struct perf_evsel *evsel;

2
tools/perf/tests/evsel-roundtrip-name.c
View file

@ -97,7 +97,7 @@ out_delete_evlist:
#define perf_evsel__name_array_test(names) \
__perf_evsel__name_array_test(names, ARRAY_SIZE(names))
int test__perf_evsel__roundtrip_name_test(int subtest __maybe_unused)
int test__perf_evsel__roundtrip_name_test(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = 0, ret = 0;

2
tools/perf/tests/evsel-tp-sched.c
View file

@ -32,7 +32,7 @@ static int perf_evsel__test_field(struct perf_evsel *evsel, const char *name,
return ret;
}
int test__perf_evsel__tp_sched_test(int subtest __maybe_unused)
int test__perf_evsel__tp_sched_test(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct perf_evsel *evsel = perf_evsel__newtp("sched", "sched_switch");
int ret = 0;

2
tools/perf/tests/expr.c
View file

@ -13,7 +13,7 @@ static int test(struct parse_ctx *ctx, const char *e, double val2)
return 0;
}
int test__expr(int subtest __maybe_unused)
int test__expr(struct test *t __maybe_unused, int subtest __maybe_unused)
{
const char *p;
const char **other;

4
tools/perf/tests/fdarray.c
View file

@ -26,7 +26,7 @@ static int fdarray__fprintf_prefix(struct fdarray *fda, const char *prefix, FILE
return printed + fdarray__fprintf(fda, fp);
}
int test__fdarray__filter(int subtest __maybe_unused)
int test__fdarray__filter(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int nr_fds, expected_fd[2], fd, err = TEST_FAIL;
struct fdarray *fda = fdarray__new(5, 5);
@ -104,7 +104,7 @@ out:
return err;
}
int test__fdarray__add(int subtest __maybe_unused)
int test__fdarray__add(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = TEST_FAIL;
struct fdarray *fda = fdarray__new(2, 2);

2
tools/perf/tests/hists_cumulate.c
View file

@ -687,7 +687,7 @@ out:
return err;
}
int test__hists_cumulate(int subtest __maybe_unused)
int test__hists_cumulate(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = TEST_FAIL;
struct machines machines;

2
tools/perf/tests/hists_filter.c
View file

@ -101,7 +101,7 @@ out:
return TEST_FAIL;
}
int test__hists_filter(int subtest __maybe_unused)
int test__hists_filter(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = TEST_FAIL;
struct machines machines;

2
tools/perf/tests/hists_link.c
View file

@ -264,7 +264,7 @@ static int validate_link(struct hists *leader, struct hists *other)
return __validate_link(leader, 0) || __validate_link(other, 1);
}
int test__hists_link(int subtest __maybe_unused)
int test__hists_link(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = -1;
struct hists *hists, *first_hists;

2
tools/perf/tests/hists_output.c
View file

@ -573,7 +573,7 @@ out:
return err;
}
int test__hists_output(int subtest __maybe_unused)
int test__hists_output(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = TEST_FAIL;
struct machines machines;

2
tools/perf/tests/is_printable_array.c
View file

@ -4,7 +4,7 @@
#include "debug.h"
#include "print_binary.h"
int test__is_printable_array(int subtest __maybe_unused)
int test__is_printable_array(struct test *test __maybe_unused, int subtest __maybe_unused)
{
char buf1[] = { 'k', 'r', 4, 'v', 'a', 0 };
char buf2[] = { 'k', 'r', 'a', 'v', 4, 0 };

2
tools/perf/tests/keep-tracking.c
View file

@ -49,7 +49,7 @@ static int find_comm(struct perf_evlist *evlist, const char *comm)
* when an event is disabled but a dummy software event is not disabled. If the
* test passes %0 is returned, otherwise %-1 is returned.
*/
int test__keep_tracking(int subtest __maybe_unused)
int test__keep_tracking(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct record_opts opts = {
.mmap_pages = UINT_MAX,

2
tools/perf/tests/kmod-path.c
View file

@ -50,7 +50,7 @@ static int test_is_kernel_module(const char *path, int cpumode, bool expect)
#define M(path, c, e) \
TEST_ASSERT_VAL("failed", !test_is_kernel_module(path, c, e))
int test__kmod_path__parse(int subtest __maybe_unused)
int test__kmod_path__parse(struct test *t __maybe_unused, int subtest __maybe_unused)
{
/* path alloc_name alloc_ext kmod comp name ext */
T("/xxxx/xxxx/x-x.ko", true , true , true, false, "[x_x]", NULL);

2
tools/perf/tests/llvm.c
View file

@ -132,7 +132,7 @@ out:
return ret;
}
int test__llvm(int subtest)
int test__llvm(struct test *test __maybe_unused, int subtest)
{
int ret;
void *obj_buf = NULL;

2
tools/perf/tests/mmap-basic.c
View file

@ -22,7 +22,7 @@
* Then it checks if the number of syscalls reported as perf events by
* the kernel corresponds to the number of syscalls made.
*/
int test__basic_mmap(int subtest __maybe_unused)
int test__basic_mmap(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = -1;
union perf_event *event;

2
tools/perf/tests/mmap-thread-lookup.c
View file

@ -221,7 +221,7 @@ static int mmap_events(synth_cb synth)
*
* by using all thread objects.
*/
int test__mmap_thread_lookup(int subtest __maybe_unused)
int test__mmap_thread_lookup(struct test *test __maybe_unused, int subtest __maybe_unused)
{
/* perf_event__synthesize_threads synthesize */
TEST_ASSERT_VAL("failed with sythesizing all",

2
tools/perf/tests/openat-syscall-all-cpus.c
View file

@ -16,7 +16,7 @@
#include "debug.h"
#include "stat.h"
int test__openat_syscall_event_on_all_cpus(int subtest __maybe_unused)
int test__openat_syscall_event_on_all_cpus(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = -1, fd, cpu;
struct cpu_map *cpus;

2
tools/perf/tests/openat-syscall-tp-fields.c
View file

@ -14,7 +14,7 @@
#define AT_FDCWD -100
#endif
int test__syscall_openat_tp_fields(int subtest __maybe_unused)
int test__syscall_openat_tp_fields(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct record_opts opts = {
.target = {

2
tools/perf/tests/openat-syscall.c
View file

@ -10,7 +10,7 @@
#include "debug.h"
#include "tests.h"
int test__openat_syscall_event(int subtest __maybe_unused)
int test__openat_syscall_event(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = -1, fd;
struct perf_evsel *evsel;

2
tools/perf/tests/parse-events.c
View file

@ -1810,7 +1810,7 @@ static int test_pmu_events(void)
return ret;
}
int test__parse_events(int subtest __maybe_unused)
int test__parse_events(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int ret1, ret2 = 0;

2
tools/perf/tests/parse-no-sample-id-all.c
View file

@ -68,7 +68,7 @@ struct test_attr_event {
*
* Return: %0 on success, %-1 if the test fails.
*/
int test__parse_no_sample_id_all(int subtest __maybe_unused)
int test__parse_no_sample_id_all(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err;

2
tools/perf/tests/perf-hooks.c
View file

@ -27,7 +27,7 @@ static void the_hook(void *_hook_flags)
*p = 0;
}
int test__perf_hooks(int subtest __maybe_unused)
int test__perf_hooks(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int hook_flags = 0;

2
tools/perf/tests/perf-record.c
View file

@ -37,7 +37,7 @@ realloc:
return cpu;
}
int test__PERF_RECORD(int subtest __maybe_unused)
int test__PERF_RECORD(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct record_opts opts = {
.target = {

2
tools/perf/tests/pmu.c
View file

@ -135,7 +135,7 @@ static struct list_head *test_terms_list(void)
return &terms;
}
int test__pmu(int subtest __maybe_unused)
int test__pmu(struct test *test __maybe_unused, int subtest __maybe_unused)
{
char *format = test_format_dir_get();
LIST_HEAD(formats);

2
tools/perf/tests/python-use.c
View file

@ -9,7 +9,7 @@
extern int verbose;
int test__python_use(int subtest __maybe_unused)
int test__python_use(struct test *test __maybe_unused, int subtest __maybe_unused)
{
char *cmd;
int ret;

2
tools/perf/tests/sample-parsing.c
View file

@ -292,7 +292,7 @@ out_free:
* checks sample format bits separately and together. If the test passes %0 is
* returned, otherwise %-1 is returned.
*/
int test__sample_parsing(int subtest __maybe_unused)
int test__sample_parsing(struct test *test __maybe_unused, int subtest __maybe_unused)
{
const u64 rf[] = {4, 5, 6, 7, 12, 13, 14, 15};
u64 sample_type;

4
tools/perf/tests/sdt.c
View file

@ -71,7 +71,7 @@ static int search_cached_probe(const char *target,
return ret;
}
int test__sdt_event(int subtests __maybe_unused)
int test__sdt_event(struct test *test __maybe_unused, int subtests __maybe_unused)
{
int ret = TEST_FAIL;
char __tempdir[] = "./test-buildid-XXXXXX";
@ -109,7 +109,7 @@ error:
return ret;
}
#else
int test__sdt_event(int subtests __maybe_unused)
int test__sdt_event(struct test *test __maybe_unused, int subtests __maybe_unused)
{
pr_debug("Skip SDT event test because SDT support is not compiled\n");
return TEST_SKIP;

28
tools/perf/tests/shell/lib/probe_vfs_getname.sh Normal file
View file

@ -0,0 +1,28 @@
# Arnaldo Carvalho de Melo <acme@kernel.org>, 2017
perf probe -l | grep -q probe:vfs_getname
had_vfs_getname=$?
cleanup_probe_vfs_getname() {
if [ $had_vfs_getname -eq 1 ] ; then
perf probe -q -d probe:vfs_getname
fi
}
add_probe_vfs_getname() {
local verbose=$1
if [ $had_vfs_getname -eq 1 ] ; then
line=$(perf probe -L getname_flags | egrep 'result.*=.*filename;' | sed -r 's/[[:space:]]+([[:digit:]]+)[[:space:]]+result->uptr.*/\1/')
perf probe $verbose "vfs_getname=getname_flags:${line} pathname=result->name:string"
fi
}
skip_if_no_debuginfo() {
add_probe_vfs_getname -v 2>&1 | grep -q "^Failed to find the path for kernel" && return 2
return 1
}
skip_if_no_debuginfo() {
add_probe_vfs_getname -v 2>&1 | grep -q "^Failed to find the path for kernel" && return 2
return 1
}

10
tools/perf/tests/shell/probe_vfs_getname.sh Executable file
View file

@ -0,0 +1,10 @@
# Add vfs_getname probe to get syscall args filenames
#
# Arnaldo Carvalho de Melo <acme@kernel.org>, 2017
. $(dirname $0)/lib/probe_vfs_getname.sh
add_probe_vfs_getname || skip_if_no_debuginfo
err=$?
cleanup_probe_vfs_getname
exit $err

37
tools/perf/tests/shell/record+script_probe_vfs_getname.sh Executable file
View file

@ -0,0 +1,37 @@
# Use vfs_getname probe to get syscall args filenames
# Uses the 'perf test shell' library to add probe:vfs_getname to the system
# then use it with 'perf record' using 'touch' to write to a temp file, then
# checks that that was captured by the vfs_getname probe in the generated
# perf.data file, with the temp file name as the pathname argument.
# Arnaldo Carvalho de Melo <acme@kernel.org>, 2017
. $(dirname $0)/lib/probe_vfs_getname.sh
perfdata=$(mktemp /tmp/__perf_test.perf.data.XXXXX)
file=$(mktemp /tmp/temporary_file.XXXXX)
record_open_file() {
echo "Recording open file:"
perf record -o ${perfdata} -e probe:vfs_getname touch $file
}
perf_script_filenames() {
echo "Looking at perf.data file for vfs_getname records for the file we touched:"
perf script -i ${perfdata} | \
egrep " +touch +[0-9]+ +\[[0-9]+\] +[0-9]+\.[0-9]+: +probe:vfs_getname: +\([[:xdigit:]]+\) +pathname=\"${file}\""
}
add_probe_vfs_getname || skip_if_no_debuginfo
err=$?
if [ $err -ne 0 ] ; then
exit $err
fi
record_open_file && perf_script_filenames
err=$?
rm -f ${perfdata}
rm -f ${file}
cleanup_probe_vfs_getname
exit $err

40
tools/perf/tests/shell/trace+probe_libc_inet_pton.sh Executable file
View file

@ -0,0 +1,40 @@
# probe libc's inet_pton & backtrace it with ping
# Installs a probe on libc's inet_pton function, that will use uprobes,
# then use 'perf trace' on a ping to localhost asking for just one packet
# with the a backtrace 3 levels deep, check that it is what we expect.
# This needs no debuginfo package, all is done using the libc ELF symtab
# and the CFI info in the binaries.
# Arnaldo Carvalho de Melo <acme@kernel.org>, 2017
trace_libc_inet_pton_backtrace() {
idx=0
expected[0]="PING.*bytes"
expected[1]="64 bytes from ::1.*"
expected[2]=".*ping statistics.*"
expected[3]=".*packets transmitted.*"
expected[4]="rtt min.*"
expected[5]="[0-9]+\.[0-9]+[[:space:]]+probe_libc:inet_pton:\([[:xdigit:]]+\)"
expected[6]=".*inet_pton[[:space:]]\(/usr/lib.*/libc-[0-9]+\.[0-9]+\.so\)$"
expected[7]="getaddrinfo[[:space:]]\(/usr/lib.*/libc-[0-9]+\.[0-9]+\.so\)$"
expected[8]=".*\(.*/bin/ping.*\)$"
perf trace --no-syscalls -e probe_libc:inet_pton/max-stack=3/ ping -6 -c 1 ::1 |& grep -v ^$ | while read line ; do
echo $line
echo "$line" | egrep -q "${expected[$idx]}"
if [ $? -ne 0 ] ; then
printf "FAIL: expected backtrace entry %d \"%s\" got \"%s\"\n" $idx "${expected[$idx]}" "$line"
exit 1
fi
let idx+=1
[ $idx -eq 9 ] && break
done
}
perf probe -q /lib64/libc-*.so inet_pton && \
trace_libc_inet_pton_backtrace
err=$?
rm -f ${file}
perf probe -q -d probe_libc:inet_pton
exit $err

31
tools/perf/tests/shell/trace+probe_vfs_getname.sh Executable file
View file

@ -0,0 +1,31 @@
# Check open filename arg using perf trace + vfs_getname
# Uses the 'perf test shell' library to add probe:vfs_getname to the system
# then use it with 'perf trace' using 'touch' to write to a temp file, then
# checks that that was captured by the vfs_getname was used by 'perf trace',
# that already handles "probe:vfs_getname" if present, and used in the
# "open" syscall "filename" argument beautifier.
# Arnaldo Carvalho de Melo <acme@kernel.org>, 2017
. $(dirname $0)/lib/probe_vfs_getname.sh
file=$(mktemp /tmp/temporary_file.XXXXX)
trace_open_vfs_getname() {
perf trace -e open touch $file 2>&1 | \
egrep " +[0-9]+\.[0-9]+ +\( +[0-9]+\.[0-9]+ ms\): +touch\/[0-9]+ open\(filename: +${file}, +flags: CREAT\|NOCTTY\|NONBLOCK\|WRONLY, +mode: +IRUGO\|IWUGO\) += +[0-9]+$"
}
add_probe_vfs_getname || skip_if_no_debuginfo
err=$?
if [ $err -ne 0 ] ; then
exit $err
fi
trace_open_vfs_getname
err=$?
rm -f ${file}
cleanup_probe_vfs_getname
exit $err

6
tools/perf/tests/stat.c
View file

@ -45,7 +45,7 @@ static int process_stat_config_event(struct perf_tool *tool __maybe_unused,
return 0;
}
int test__synthesize_stat_config(int subtest __maybe_unused)
int test__synthesize_stat_config(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct perf_stat_config stat_config = {
.aggr_mode = AGGR_CORE,
@ -75,7 +75,7 @@ static int process_stat_event(struct perf_tool *tool __maybe_unused,
return 0;
}
int test__synthesize_stat(int subtest __maybe_unused)
int test__synthesize_stat(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct perf_counts_values count;
@ -101,7 +101,7 @@ static int process_stat_round_event(struct perf_tool *tool __maybe_unused,
return 0;
}
int test__synthesize_stat_round(int subtest __maybe_unused)
int test__synthesize_stat_round(struct test *test __maybe_unused, int subtest __maybe_unused)
{
TEST_ASSERT_VAL("failed to synthesize stat_config",
!perf_event__synthesize_stat_round(NULL, 0xdeadbeef, PERF_STAT_ROUND_TYPE__INTERVAL,

2
tools/perf/tests/sw-clock.c
View file

@ -124,7 +124,7 @@ out_delete_evlist:
return err;
}
int test__sw_clock_freq(int subtest __maybe_unused)
int test__sw_clock_freq(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int ret;

2
tools/perf/tests/switch-tracking.c
View file

@ -306,7 +306,7 @@ out_free_nodes:
* evsel->system_wide and evsel->tracking flags (respectively) with other events
* sometimes enabled or disabled.
*/
int test__switch_tracking(int subtest __maybe_unused)
int test__switch_tracking(struct test *test __maybe_unused, int subtest __maybe_unused)
{
const char *sched_switch = "sched:sched_switch";
struct switch_tracking switch_tracking = { .tids = NULL, };

2
tools/perf/tests/task-exit.c
View file

@ -32,7 +32,7 @@ static void workload_exec_failed_signal(int signo __maybe_unused,
* if the number of exit event reported by the kernel is 1 or not
* in order to check the kernel returns correct number of event.
*/
int test__task_exit(int subtest __maybe_unused)
int test__task_exit(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = -1;
union perf_event *event;

113
tools/perf/tests/tests.h
View file

@ -28,77 +28,78 @@ enum {
struct test {
const char *desc;
int (*func)(int subtest);
int (*func)(struct test *test, int subtest);
struct {
bool skip_if_fail;
int (*get_nr)(void);
const char *(*get_desc)(int subtest);
} subtest;
bool (*is_supported)(void);
void *priv;
};
/* Tests */
int test__vmlinux_matches_kallsyms(int subtest);
int test__openat_syscall_event(int subtest);
int test__openat_syscall_event_on_all_cpus(int subtest);
int test__basic_mmap(int subtest);
int test__PERF_RECORD(int subtest);
int test__perf_evsel__roundtrip_name_test(int subtest);
int test__perf_evsel__tp_sched_test(int subtest);
int test__syscall_openat_tp_fields(int subtest);
int test__pmu(int subtest);
int test__attr(int subtest);
int test__dso_data(int subtest);
int test__dso_data_cache(int subtest);
int test__dso_data_reopen(int subtest);
int test__parse_events(int subtest);
int test__hists_link(int subtest);
int test__python_use(int subtest);
int test__bp_signal(int subtest);
int test__bp_signal_overflow(int subtest);
int test__task_exit(int subtest);
int test__sw_clock_freq(int subtest);
int test__code_reading(int subtest);
int test__sample_parsing(int subtest);
int test__keep_tracking(int subtest);
int test__parse_no_sample_id_all(int subtest);
int test__dwarf_unwind(int subtest);
int test__expr(int subtest);
int test__hists_filter(int subtest);
int test__mmap_thread_lookup(int subtest);
int test__thread_mg_share(int subtest);
int test__hists_output(int subtest);
int test__hists_cumulate(int subtest);
int test__switch_tracking(int subtest);
int test__fdarray__filter(int subtest);
int test__fdarray__add(int subtest);
int test__kmod_path__parse(int subtest);
int test__thread_map(int subtest);
int test__llvm(int subtest);
int test__vmlinux_matches_kallsyms(struct test *test, int subtest);
int test__openat_syscall_event(struct test *test, int subtest);
int test__openat_syscall_event_on_all_cpus(struct test *test, int subtest);
int test__basic_mmap(struct test *test, int subtest);
int test__PERF_RECORD(struct test *test, int subtest);
int test__perf_evsel__roundtrip_name_test(struct test *test, int subtest);
int test__perf_evsel__tp_sched_test(struct test *test, int subtest);
int test__syscall_openat_tp_fields(struct test *test, int subtest);
int test__pmu(struct test *test, int subtest);
int test__attr(struct test *test, int subtest);
int test__dso_data(struct test *test, int subtest);
int test__dso_data_cache(struct test *test, int subtest);
int test__dso_data_reopen(struct test *test, int subtest);
int test__parse_events(struct test *test, int subtest);
int test__hists_link(struct test *test, int subtest);
int test__python_use(struct test *test, int subtest);
int test__bp_signal(struct test *test, int subtest);
int test__bp_signal_overflow(struct test *test, int subtest);
int test__task_exit(struct test *test, int subtest);
int test__sw_clock_freq(struct test *test, int subtest);
int test__code_reading(struct test *test, int subtest);
int test__sample_parsing(struct test *test, int subtest);
int test__keep_tracking(struct test *test, int subtest);
int test__parse_no_sample_id_all(struct test *test, int subtest);
int test__dwarf_unwind(struct test *test, int subtest);
int test__expr(struct test *test, int subtest);
int test__hists_filter(struct test *test, int subtest);
int test__mmap_thread_lookup(struct test *test, int subtest);
int test__thread_mg_share(struct test *test, int subtest);
int test__hists_output(struct test *test, int subtest);
int test__hists_cumulate(struct test *test, int subtest);
int test__switch_tracking(struct test *test, int subtest);
int test__fdarray__filter(struct test *test, int subtest);
int test__fdarray__add(struct test *test, int subtest);
int test__kmod_path__parse(struct test *test, int subtest);
int test__thread_map(struct test *test, int subtest);
int test__llvm(struct test *test, int subtest);
const char *test__llvm_subtest_get_desc(int subtest);
int test__llvm_subtest_get_nr(void);
int test__bpf(int subtest);
int test__bpf(struct test *test, int subtest);
const char *test__bpf_subtest_get_desc(int subtest);
int test__bpf_subtest_get_nr(void);
int test_session_topology(int subtest);
int test__thread_map_synthesize(int subtest);
int test__thread_map_remove(int subtest);
int test__cpu_map_synthesize(int subtest);
int test__synthesize_stat_config(int subtest);
int test__synthesize_stat(int subtest);
int test__synthesize_stat_round(int subtest);
int test__event_update(int subtest);
int test__event_times(int subtest);
int test__backward_ring_buffer(int subtest);
int test__cpu_map_print(int subtest);
int test__sdt_event(int subtest);
int test__is_printable_array(int subtest);
int test__bitmap_print(int subtest);
int test__perf_hooks(int subtest);
int test__clang(int subtest);
int test__session_topology(struct test *test, int subtest);
int test__thread_map_synthesize(struct test *test, int subtest);
int test__thread_map_remove(struct test *test, int subtest);
int test__cpu_map_synthesize(struct test *test, int subtest);
int test__synthesize_stat_config(struct test *test, int subtest);
int test__synthesize_stat(struct test *test, int subtest);
int test__synthesize_stat_round(struct test *test, int subtest);
int test__event_update(struct test *test, int subtest);
int test__event_times(struct test *test, int subtest);
int test__backward_ring_buffer(struct test *test, int subtest);
int test__cpu_map_print(struct test *test, int subtest);
int test__sdt_event(struct test *test, int subtest);
int test__is_printable_array(struct test *test, int subtest);
int test__bitmap_print(struct test *test, int subtest);
int test__perf_hooks(struct test *test, int subtest);
int test__clang(struct test *test, int subtest);
const char *test__clang_subtest_get_desc(int subtest);
int test__clang_subtest_get_nr(void);
int test__unit_number__scnprint(int subtest);
int test__unit_number__scnprint(struct test *test, int subtest);
bool test__bp_signal_is_supported(void);

6
tools/perf/tests/thread-map.c
View file

@ -9,7 +9,7 @@
#define NAME (const char *) "perf"
#define NAMEUL (unsigned long) NAME
int test__thread_map(int subtest __maybe_unused)
int test__thread_map(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct thread_map *map;
@ -76,7 +76,7 @@ static int process_event(struct perf_tool *tool __maybe_unused,
return 0;
}
int test__thread_map_synthesize(int subtest __maybe_unused)
int test__thread_map_synthesize(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct thread_map *threads;
@ -95,7 +95,7 @@ int test__thread_map_synthesize(int subtest __maybe_unused)
return 0;
}
int test__thread_map_remove(int subtest __maybe_unused)
int test__thread_map_remove(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct thread_map *threads;
char *str;

2
tools/perf/tests/thread-mg-share.c
View file

@ -4,7 +4,7 @@
#include "map.h"
#include "debug.h"
int test__thread_mg_share(int subtest __maybe_unused)
int test__thread_mg_share(struct test *test __maybe_unused, int subtest __maybe_unused)
{
struct machines machines;
struct machine *machine;

2
tools/perf/tests/topology.c
View file

@ -86,7 +86,7 @@ static int check_cpu_topology(char *path, struct cpu_map *map)
return 0;
}
int test_session_topology(int subtest __maybe_unused)
int test__session_topology(struct test *test __maybe_unused, int subtest __maybe_unused)
{
char path[PATH_MAX];
struct cpu_map *map;

2
tools/perf/tests/unit_number__scnprintf.c
View file

@ -5,7 +5,7 @@
#include "units.h"
#include "debug.h"
int test__unit_number__scnprint(int subtest __maybe_unused)
int test__unit_number__scnprint(struct test *t __maybe_unused, int subtest __maybe_unused)
{
struct {
u64 n;

2
tools/perf/tests/vmlinux-kallsyms.c
View file

@ -11,7 +11,7 @@
#define UM(x) kallsyms_map->unmap_ip(kallsyms_map, (x))
int test__vmlinux_matches_kallsyms(int subtest __maybe_unused)
int test__vmlinux_matches_kallsyms(struct test *test __maybe_unused, int subtest __maybe_unused)
{
int err = -1;
struct rb_node *nd;

2
tools/perf/util/expr.y
View file

@ -62,7 +62,7 @@ all_expr: expr { *final_val = $1; }
expr: NUMBER
| ID { if (lookup_id(ctx, $1, &$$) < 0) {
pr_debug("%s not found", $1);
pr_debug("%s not found\n", $1);
YYABORT;
}
}

4
tools/perf/util/machine.c
View file

@ -1138,7 +1138,8 @@ int __weak arch__fix_module_text_start(u64 *start __maybe_unused,
return 0;
}
static int machine__create_module(void *arg, const char *name, u64 start)
static int machine__create_module(void *arg, const char *name, u64 start,
u64 size)
{
struct machine *machine = arg;
struct map *map;
@ -1149,6 +1150,7 @@ static int machine__create_module(void *arg, const char *name, u64 start)
map = machine__findnew_module_map(machine, start, name);
if (map == NULL)
return -1;
map->end = start + size;
dso__kernel_module_get_build_id(map->dso, machine->root_dir);

6
tools/perf/util/srcline.c
View file

@ -155,6 +155,9 @@ static void find_address_in_section(bfd *abfd, asection *section, void *data)
a2l->found = bfd_find_nearest_line(abfd, section, a2l->syms, pc - vma,
&a2l->filename, &a2l->funcname,
&a2l->line);
if (a2l->filename && !strlen(a2l->filename))
a2l->filename = NULL;
}
static struct a2l_data *addr2line_init(const char *path)
@ -248,6 +251,9 @@ static int addr2line(const char *dso_name, u64 addr,
&a2l->funcname, &a2l->line) &&
cnt++ < MAX_INLINE_NEST) {
if (a2l->filename && !strlen(a2l->filename))
a2l->filename = NULL;
if (node != NULL) {
if (inline_list__append_dso_a2l(dso, node))
return 0;

6
tools/perf/util/stat-shadow.c
View file

@ -70,7 +70,11 @@ static int saved_value_cmp(struct rb_node *rb_node, const void *entry)
return a->ctx - b->ctx;
if (a->cpu != b->cpu)
return a->cpu - b->cpu;
return a->evsel - b->evsel;
if (a->evsel == b->evsel)
return 0;
if ((char *)a->evsel < (char *)b->evsel)
return -1;
return +1;
}
static struct rb_node *saved_value_new(struct rblist *rblist __maybe_unused,

12
tools/perf/util/symbol-elf.c
View file

@ -391,7 +391,7 @@ out_elf_end:
return 0;
}
char *dso__demangle_sym(struct dso *dso, int kmodule, char *elf_name)
char *dso__demangle_sym(struct dso *dso, int kmodule, const char *elf_name)
{
return demangle_sym(dso, kmodule, elf_name);
}
@ -793,6 +793,12 @@ static u64 ref_reloc(struct kmap *kmap)
void __weak arch__sym_update(struct symbol *s __maybe_unused,
GElf_Sym *sym __maybe_unused) { }
void __weak arch__adjust_sym_map_offset(GElf_Sym *sym, GElf_Shdr *shdr,
struct map *map __maybe_unused)
{
sym->st_value -= shdr->sh_addr - shdr->sh_offset;
}
int dso__load_sym(struct dso *dso, struct map *map, struct symsrc *syms_ss,
struct symsrc *runtime_ss, int kmodule)
{
@ -973,7 +979,7 @@ int dso__load_sym(struct dso *dso, struct map *map, struct symsrc *syms_ss,
/* Adjust symbol to map to file offset */
if (adjust_kernel_syms)
sym.st_value -= shdr.sh_addr - shdr.sh_offset;
arch__adjust_sym_map_offset(&sym, &shdr, map);
if (strcmp(section_name,
(curr_dso->short_name +
@ -1442,7 +1448,7 @@ static int kcore_copy__parse_kallsyms(struct kcore_copy_info *kci,
static int kcore_copy__process_modules(void *arg,
const char *name __maybe_unused,
u64 start)
u64 start, u64 size __maybe_unused)
{
struct kcore_copy_info *kci = arg;

2
tools/perf/util/symbol-minimal.c
View file

@ -377,7 +377,7 @@ void symbol__elf_init(void)
char *dso__demangle_sym(struct dso *dso __maybe_unused,
int kmodule __maybe_unused,
char *elf_name __maybe_unused)
const char *elf_name __maybe_unused)
{
return NULL;
}

21
tools/perf/util/symbol.c
View file

@ -233,7 +233,8 @@ void __map_groups__fixup_end(struct map_groups *mg, enum map_type type)
goto out_unlock;
for (next = map__next(curr); next; next = map__next(curr)) {
curr->end = next->start;
if (!curr->end)
curr->end = next->start;
curr = next;
}
@ -241,7 +242,8 @@ void __map_groups__fixup_end(struct map_groups *mg, enum map_type type)
* We still haven't the actual symbols, so guess the
* last map final address.
*/
curr->end = ~0ULL;
if (!curr->end)
curr->end = ~0ULL;
out_unlock:
pthread_rwlock_unlock(&maps->lock);
@ -552,7 +554,7 @@ void dso__sort_by_name(struct dso *dso, enum map_type type)
int modules__parse(const char *filename, void *arg,
int (*process_module)(void *arg, const char *name,
u64 start))
u64 start, u64 size))
{
char *line = NULL;
size_t n;
@ -565,8 +567,8 @@ int modules__parse(const char *filename, void *arg,
while (1) {
char name[PATH_MAX];
u64 start;
char *sep;
u64 start, size;
char *sep, *endptr;
ssize_t line_len;
line_len = getline(&line, &n, file);
@ -598,7 +600,11 @@ int modules__parse(const char *filename, void *arg,
scnprintf(name, sizeof(name), "[%s]", line);
err = process_module(arg, name, start);
size = strtoul(sep + 1, &endptr, 0);
if (*endptr != ' ' && *endptr != '\t')
continue;
err = process_module(arg, name, start, size);
if (err)
break;
}
@ -945,7 +951,8 @@ static struct module_info *find_module(const char *name,
return NULL;
}
static int __read_proc_modules(void *arg, const char *name, u64 start)
static int __read_proc_modules(void *arg, const char *name, u64 start,
u64 size __maybe_unused)
{
struct rb_root *modules = arg;
struct module_info *mi;

7
tools/perf/util/symbol.h
View file

@ -273,7 +273,7 @@ int filename__read_build_id(const char *filename, void *bf, size_t size);
int sysfs__read_build_id(const char *filename, void *bf, size_t size);
int modules__parse(const char *filename, void *arg,
int (*process_module)(void *arg, const char *name,
u64 start));
u64 start, u64 size));
int filename__read_debuglink(const char *filename, char *debuglink,
size_t size);
@ -306,7 +306,7 @@ int dso__load_sym(struct dso *dso, struct map *map, struct symsrc *syms_ss,
int dso__synthesize_plt_symbols(struct dso *dso, struct symsrc *ss,
struct map *map);
char *dso__demangle_sym(struct dso *dso, int kmodule, char *elf_name);
char *dso__demangle_sym(struct dso *dso, int kmodule, const char *elf_name);
void __symbols__insert(struct rb_root *symbols, struct symbol *sym, bool kernel);
void symbols__insert(struct rb_root *symbols, struct symbol *sym);
@ -343,6 +343,9 @@ int setup_intlist(struct intlist **list, const char *list_str,
#ifdef HAVE_LIBELF_SUPPORT
bool elf__needs_adjust_symbols(GElf_Ehdr ehdr);
void arch__sym_update(struct symbol *s, GElf_Sym *sym);
void arch__adjust_sym_map_offset(GElf_Sym *sym,
GElf_Shdr *shdr __maybe_unused,
struct map *map __maybe_unused);
#endif
#define SYMBOL_A 0