spi: davinci: remove non-useful interrupt mode support
The interrupt mode support as it stands is another version of poll mode. Even when interrupt mode is selected, the code tight loops on interrupt status register, rendering it totally useless. A completion variable is initialized, but never used. Remove this fake interrupt mode since users can anyway use poll mode with no functional difference. A usefully implemented interrupt mode support can be added later. Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com> Tested-By: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>hifive-unleashed-5.1
Brian Niebuhr
Sekhar Nori
parent
47f44671c0
commit
cf90fe7350
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@ -413,7 +413,6 @@ static struct davinci_spi_platform_data dm355_spi0_pdata = {
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.version = SPI_VERSION_1,
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.num_chipselect = 2,
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.clk_internal = 1,
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.poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
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};
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static struct platform_device dm355_spi0_device = {
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.name = "spi_davinci",
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@ -626,7 +626,6 @@ static struct davinci_spi_platform_data dm365_spi0_pdata = {
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.version = SPI_VERSION_1,
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.num_chipselect = 2,
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.clk_internal = 1,
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.poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
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};
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static struct resource dm365_spi0_resources[] = {
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@ -30,8 +30,6 @@ struct davinci_spi_platform_data {
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u8 version;
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u8 num_chipselect;
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u8 clk_internal;
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u8 intr_level;
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u8 poll_mode;
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u8 use_dma;
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u8 *chip_sel;
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};
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@ -59,8 +59,6 @@
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#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
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#define SPIINT_MASKALL 0x0101035F
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#define SPI_INTLVL_1 0x000001FFu
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#define SPI_INTLVL_0 0x00000000u
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/* SPIDAT1 (upper 16 bit defines) */
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#define SPIDAT1_CSHOLD_MASK BIT(12)
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@ -92,14 +90,8 @@
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#define SPIFLG_DESYNC_MASK BIT(3)
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#define SPIFLG_BITERR_MASK BIT(4)
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#define SPIFLG_OVRRUN_MASK BIT(6)
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#define SPIFLG_RX_INTR_MASK BIT(8)
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#define SPIFLG_TX_INTR_MASK BIT(9)
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#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
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#define SPIINT_BITERR_INTR BIT(4)
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#define SPIINT_OVRRUN_INTR BIT(6)
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#define SPIINT_RX_INTR BIT(8)
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#define SPIINT_TX_INTR BIT(9)
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#define SPIINT_DMA_REQ_EN BIT(16)
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/* SPI Controller registers */
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@ -136,8 +128,6 @@ struct davinci_spi {
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resource_size_t pbase;
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void __iomem *base;
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size_t region_size;
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u32 irq;
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struct completion done;
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const void *tx;
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void *rx;
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@ -611,7 +601,7 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
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static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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{
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struct davinci_spi *davinci_spi;
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int int_status, count, ret;
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int status, count, ret;
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u8 conv;
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u32 tx_data, data1_reg_val;
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u32 buf_val, flg_val;
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@ -627,8 +617,6 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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conv = davinci_spi->bytes_per_word[spi->chip_select];
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data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
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INIT_COMPLETION(davinci_spi->done);
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ret = davinci_spi_bufs_prep(spi, davinci_spi);
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if (ret)
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return ret;
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@ -638,9 +626,10 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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count = t->len / conv;
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
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/* Determine the command to execute READ or WRITE */
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if (t->tx_buf) {
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
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while (1) {
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tx_data = davinci_spi->get_tx(davinci_spi);
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@ -668,45 +657,25 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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break;
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}
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} else {
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if (pdata->poll_mode) {
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while (1) {
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/* keeps the serial clock going */
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if ((ioread32(davinci_spi->base + SPIBUF)
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& SPIBUF_TXFULL_MASK) == 0)
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iowrite32(data1_reg_val,
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davinci_spi->base + SPIDAT1);
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while (1) {
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/* keeps the serial clock going */
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if ((ioread32(davinci_spi->base + SPIBUF)
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& SPIBUF_TXFULL_MASK) == 0)
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iowrite32(data1_reg_val,
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davinci_spi->base + SPIDAT1);
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while (ioread32(davinci_spi->base + SPIBUF) &
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SPIBUF_RXEMPTY_MASK)
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SPIBUF_RXEMPTY_MASK)
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cpu_relax();
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flg_val = ioread32(davinci_spi->base + SPIFLG);
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buf_val = ioread32(davinci_spi->base + SPIBUF);
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flg_val = ioread32(davinci_spi->base + SPIFLG);
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buf_val = ioread32(davinci_spi->base + SPIBUF);
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davinci_spi->get_rx(buf_val, davinci_spi);
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davinci_spi->get_rx(buf_val, davinci_spi);
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count--;
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if (count <= 0)
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break;
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}
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} else { /* Receive in Interrupt mode */
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int i;
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for (i = 0; i < count; i++) {
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set_io_bits(davinci_spi->base + SPIINT,
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SPIINT_BITERR_INTR
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| SPIINT_OVRRUN_INTR
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| SPIINT_RX_INTR);
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iowrite32(data1_reg_val,
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davinci_spi->base + SPIDAT1);
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while (ioread32(davinci_spi->base + SPIINT) &
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SPIINT_RX_INTR)
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cpu_relax();
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}
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iowrite32((data1_reg_val & 0x0ffcffff),
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davinci_spi->base + SPIDAT1);
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count--;
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if (count <= 0)
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break;
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}
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}
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@ -714,9 +683,9 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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* Check for bit error, desync error,parity error,timeout error and
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* receive overflow errors
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*/
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int_status = ioread32(davinci_spi->base + SPIFLG);
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status = ioread32(davinci_spi->base + SPIFLG);
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ret = davinci_spi_check_error(davinci_spi, int_status);
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ret = davinci_spi_check_error(davinci_spi, status);
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if (ret != 0)
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return ret;
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@ -853,38 +822,6 @@ static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
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return t->len;
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}
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/**
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* davinci_spi_irq - IRQ handler for DaVinci SPI
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* @irq: IRQ number for this SPI Master
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* @context_data: structure for SPI Master controller davinci_spi
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*/
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static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
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{
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struct davinci_spi *davinci_spi = context_data;
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u32 int_status, rx_data = 0;
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irqreturn_t ret = IRQ_NONE;
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int_status = ioread32(davinci_spi->base + SPIFLG);
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while ((int_status & SPIFLG_RX_INTR_MASK)) {
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if (likely(int_status & SPIFLG_RX_INTR_MASK)) {
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ret = IRQ_HANDLED;
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rx_data = ioread32(davinci_spi->base + SPIBUF);
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davinci_spi->get_rx(rx_data, davinci_spi);
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/* Disable Receive Interrupt */
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iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR),
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davinci_spi->base + SPIINT);
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} else
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(void)davinci_spi_check_error(davinci_spi, int_status);
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int_status = ioread32(davinci_spi->base + SPIFLG);
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}
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return ret;
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}
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/**
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* davinci_spi_probe - probe function for SPI Master Controller
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* @pdev: platform_device structure which contains plateform specific data
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@ -943,22 +880,11 @@ static int davinci_spi_probe(struct platform_device *pdev)
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goto release_region;
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}
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davinci_spi->irq = platform_get_irq(pdev, 0);
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if (davinci_spi->irq <= 0) {
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ret = -EINVAL;
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goto unmap_io;
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}
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ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
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dev_name(&pdev->dev), davinci_spi);
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if (ret)
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goto unmap_io;
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/* Allocate tmp_buf for tx_buf */
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davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
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if (davinci_spi->tmp_buf == NULL) {
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ret = -ENOMEM;
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goto irq_free;
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goto unmap_io;
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}
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davinci_spi->bitbang.master = spi_master_get(master);
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@ -1034,8 +960,6 @@ static int davinci_spi_probe(struct platform_device *pdev)
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davinci_spi->get_rx = davinci_spi_rx_buf_u8;
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davinci_spi->get_tx = davinci_spi_tx_buf_u8;
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init_completion(&davinci_spi->done);
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/* Reset In/OUT SPI module */
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iowrite32(0, davinci_spi->base + SPIGCR0);
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udelay(100);
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@ -1062,21 +986,12 @@ static int davinci_spi_probe(struct platform_device *pdev)
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/* master mode default */
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
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if (davinci_spi->pdata->intr_level)
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iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
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else
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iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
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ret = spi_bitbang_start(&davinci_spi->bitbang);
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if (ret)
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goto free_clk;
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dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
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if (!pdata->poll_mode)
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dev_info(&pdev->dev, "Operating in interrupt mode"
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" using IRQ %d\n", davinci_spi->irq);
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return ret;
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free_clk:
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@ -1086,8 +1001,6 @@ put_master:
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spi_master_put(master);
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free_tmp_buf:
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kfree(davinci_spi->tmp_buf);
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irq_free:
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free_irq(davinci_spi->irq, davinci_spi);
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unmap_io:
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iounmap(davinci_spi->base);
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release_region:
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@ -1121,7 +1034,6 @@ static int __exit davinci_spi_remove(struct platform_device *pdev)
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clk_put(davinci_spi->clk);
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spi_master_put(master);
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kfree(davinci_spi->tmp_buf);
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free_irq(davinci_spi->irq, davinci_spi);
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iounmap(davinci_spi->base);
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release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
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