drm/i915: Allow fuzzy matching in pipe_config_compare, v2.
Instead of doing ad-hoc checks we already have a way of checking if the state is compatible or not. Use this to force a modeset. Only during modesets, or with PIPE_CONFIG_QUIRK_INHERITED_MODE we should check if a full modeset is really needed. Fastboot will allow the adjust parameter to ignore some stuff too, and it will fix up differences in state that are ignored by the compare function. Changes since v1: - Increase the value of the lowest m/n to prevent truncation. - Dump pipe config when fastboot's used, without a modeset. - Add adjust parameter to intel_compare_link_m_n, which is used to adjust m2_n2 if it's a multiple of m_n. - Add exact parameter intel_compare_m_n. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
parent
8e9ba31a0f
commit
cfb23ed622
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@ -12288,19 +12288,6 @@ encoder_retry:
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DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
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base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
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/* Check if we need to force a modeset */
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if (pipe_config->has_audio !=
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to_intel_crtc_state(crtc->state)->has_audio) {
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pipe_config->base.mode_changed = true;
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ret = drm_atomic_add_affected_planes(state, crtc);
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}
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/*
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* Note we have an issue here with infoframes: current code
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* only updates them on the full mode set path per hw
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* requirements. So here we should be checking for any
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* required changes and forcing a mode set.
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*/
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fail:
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return ret;
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}
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@ -12404,27 +12391,133 @@ static bool intel_fuzzy_clock_check(int clock1, int clock2)
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base.head) \
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if (mask & (1 <<(intel_crtc)->pipe))
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static bool
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intel_compare_m_n(unsigned int m, unsigned int n,
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unsigned int m2, unsigned int n2,
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bool exact)
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{
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if (m == m2 && n == n2)
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return true;
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if (exact || !m || !n || !m2 || !n2)
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return false;
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BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
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if (m > m2) {
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while (m > m2) {
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m2 <<= 1;
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n2 <<= 1;
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}
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} else if (m < m2) {
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while (m < m2) {
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m <<= 1;
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n <<= 1;
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}
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}
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return m == m2 && n == n2;
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}
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static bool
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intel_compare_link_m_n(const struct intel_link_m_n *m_n,
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struct intel_link_m_n *m2_n2,
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bool adjust)
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{
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if (m_n->tu == m2_n2->tu &&
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intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
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m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
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intel_compare_m_n(m_n->link_m, m_n->link_n,
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m2_n2->link_m, m2_n2->link_n, !adjust)) {
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if (adjust)
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*m2_n2 = *m_n;
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return true;
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}
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return false;
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}
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static bool
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intel_pipe_config_compare(struct drm_device *dev,
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struct intel_crtc_state *current_config,
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struct intel_crtc_state *pipe_config)
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struct intel_crtc_state *pipe_config,
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bool adjust)
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{
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bool ret = true;
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#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
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do { \
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if (!adjust) \
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DRM_ERROR(fmt, ##__VA_ARGS__); \
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else \
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DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
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} while (0)
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#define PIPE_CONF_CHECK_X(name) \
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if (current_config->name != pipe_config->name) { \
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DRM_ERROR("mismatch in " #name " " \
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INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
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"(expected 0x%08x, found 0x%08x)\n", \
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current_config->name, \
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pipe_config->name); \
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return false; \
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ret = false; \
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}
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#define PIPE_CONF_CHECK_I(name) \
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if (current_config->name != pipe_config->name) { \
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DRM_ERROR("mismatch in " #name " " \
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INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
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"(expected %i, found %i)\n", \
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current_config->name, \
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pipe_config->name); \
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return false; \
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ret = false; \
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}
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#define PIPE_CONF_CHECK_M_N(name) \
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if (!intel_compare_link_m_n(¤t_config->name, \
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&pipe_config->name,\
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adjust)) { \
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INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
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"(expected tu %i gmch %i/%i link %i/%i, " \
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"found tu %i, gmch %i/%i link %i/%i)\n", \
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current_config->name.tu, \
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current_config->name.gmch_m, \
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current_config->name.gmch_n, \
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current_config->name.link_m, \
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current_config->name.link_n, \
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pipe_config->name.tu, \
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pipe_config->name.gmch_m, \
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pipe_config->name.gmch_n, \
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pipe_config->name.link_m, \
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pipe_config->name.link_n); \
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ret = false; \
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}
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#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
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if (!intel_compare_link_m_n(¤t_config->name, \
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&pipe_config->name, adjust) && \
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!intel_compare_link_m_n(¤t_config->alt_name, \
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&pipe_config->name, adjust)) { \
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INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
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"(expected tu %i gmch %i/%i link %i/%i, " \
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"or tu %i gmch %i/%i link %i/%i, " \
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"found tu %i, gmch %i/%i link %i/%i)\n", \
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current_config->name.tu, \
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current_config->name.gmch_m, \
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current_config->name.gmch_n, \
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current_config->name.link_m, \
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current_config->name.link_n, \
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current_config->alt_name.tu, \
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current_config->alt_name.gmch_m, \
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current_config->alt_name.gmch_n, \
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current_config->alt_name.link_m, \
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current_config->alt_name.link_n, \
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pipe_config->name.tu, \
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pipe_config->name.gmch_m, \
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pipe_config->name.gmch_n, \
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pipe_config->name.link_m, \
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pipe_config->name.link_n); \
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ret = false; \
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}
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/* This is required for BDW+ where there is only one set of registers for
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@ -12435,30 +12528,30 @@ intel_pipe_config_compare(struct drm_device *dev,
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#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
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if ((current_config->name != pipe_config->name) && \
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(current_config->alt_name != pipe_config->name)) { \
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DRM_ERROR("mismatch in " #name " " \
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INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
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"(expected %i or %i, found %i)\n", \
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current_config->name, \
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current_config->alt_name, \
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pipe_config->name); \
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return false; \
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ret = false; \
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}
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#define PIPE_CONF_CHECK_FLAGS(name, mask) \
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if ((current_config->name ^ pipe_config->name) & (mask)) { \
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DRM_ERROR("mismatch in " #name "(" #mask ") " \
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INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
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"(expected %i, found %i)\n", \
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current_config->name & (mask), \
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pipe_config->name & (mask)); \
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return false; \
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ret = false; \
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}
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#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
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if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
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DRM_ERROR("mismatch in " #name " " \
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INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
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"(expected %i, found %i)\n", \
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current_config->name, \
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pipe_config->name); \
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return false; \
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ret = false; \
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}
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#define PIPE_CONF_QUIRK(quirk) \
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@ -12468,35 +12561,18 @@ intel_pipe_config_compare(struct drm_device *dev,
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PIPE_CONF_CHECK_I(has_pch_encoder);
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PIPE_CONF_CHECK_I(fdi_lanes);
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PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
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PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
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PIPE_CONF_CHECK_I(fdi_m_n.link_m);
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PIPE_CONF_CHECK_I(fdi_m_n.link_n);
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PIPE_CONF_CHECK_I(fdi_m_n.tu);
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PIPE_CONF_CHECK_M_N(fdi_m_n);
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PIPE_CONF_CHECK_I(has_dp_encoder);
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if (INTEL_INFO(dev)->gen < 8) {
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PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
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PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
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PIPE_CONF_CHECK_I(dp_m_n.link_m);
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PIPE_CONF_CHECK_I(dp_m_n.link_n);
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PIPE_CONF_CHECK_I(dp_m_n.tu);
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PIPE_CONF_CHECK_M_N(dp_m_n);
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if (current_config->has_drrs) {
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PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
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PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
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PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
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PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
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PIPE_CONF_CHECK_I(dp_m2_n2.tu);
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}
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} else {
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PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
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PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
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PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
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PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
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PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
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}
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PIPE_CONF_CHECK_I(has_drrs);
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if (current_config->has_drrs)
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PIPE_CONF_CHECK_M_N(dp_m2_n2);
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} else
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PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
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@ -12592,8 +12668,9 @@ intel_pipe_config_compare(struct drm_device *dev,
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#undef PIPE_CONF_CHECK_FLAGS
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#undef PIPE_CONF_CHECK_CLOCK_FUZZY
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#undef PIPE_CONF_QUIRK
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#undef INTEL_ERR_OR_DBG_KMS
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return true;
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return ret;
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}
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static void check_wm_state(struct drm_device *dev)
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@ -12785,8 +12862,11 @@ check_crtc_state(struct drm_device *dev)
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"transitional active state does not match atomic hw state "
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"(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
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if (active &&
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!intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
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if (!active)
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continue;
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if (!intel_pipe_config_compare(dev, crtc->config,
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&pipe_config, false)) {
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I915_STATE_WARN(1, "pipe state doesn't match!\n");
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intel_dump_pipe_config(crtc, &pipe_config,
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"[hw state]");
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@ -13087,14 +13167,17 @@ intel_modeset_compute_config(struct drm_atomic_state *state)
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return ret;
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for_each_crtc_in_state(state, crtc, crtc_state, i) {
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struct intel_crtc_state *pipe_config =
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to_intel_crtc_state(crtc_state);
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bool modeset, recalc;
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if (!crtc_state->enable) {
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if (needs_modeset(crtc_state))
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any_ms = true;
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continue;
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}
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if (to_intel_crtc_state(crtc_state)->quirks &
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PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
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if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
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ret = drm_atomic_add_affected_planes(state, crtc);
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if (ret)
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return ret;
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@ -13107,23 +13190,36 @@ intel_modeset_compute_config(struct drm_atomic_state *state)
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*/
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}
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if (!needs_modeset(crtc_state)) {
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modeset = needs_modeset(crtc_state);
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recalc = pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE;
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if (!modeset && !recalc)
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continue;
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if (recalc) {
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ret = drm_atomic_add_affected_connectors(state, crtc);
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if (ret)
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return ret;
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}
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ret = intel_modeset_pipe_config(crtc,
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to_intel_crtc_state(crtc_state));
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ret = intel_modeset_pipe_config(crtc, pipe_config);
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if (ret)
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return ret;
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if (needs_modeset(crtc_state))
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any_ms = true;
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if (recalc && !intel_pipe_config_compare(state->dev,
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to_intel_crtc_state(crtc->state),
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pipe_config, true)) {
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modeset = crtc_state->mode_changed = true;
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ret = drm_atomic_add_affected_planes(state, crtc);
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if (ret)
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return ret;
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}
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any_ms = modeset;
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intel_dump_pipe_config(to_intel_crtc(crtc),
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to_intel_crtc_state(crtc_state),
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"[modeset]");
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pipe_config,
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modeset ? "[modeset]" : "[fastboot]");
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}
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if (any_ms) {
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