Blackfin: BF54x: punt useless "masks" for count/address MMRs
There's no point in having mask defines when the entire MMR value is a count or address. i.e. applying a mask of -1 is pointless. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -1815,10 +1815,6 @@
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#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
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#define CORE_MERROR 0x80 /* Core Error (2nd) */
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/* Bit masks for EBIU_ERRADD */
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#define ERROR_ADDRESS 0xffffffff /* Error Address */
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/* Bit masks for EBIU_RSTCTL */
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#define DDRSRESET 0x1 /* DDR soft reset */
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@ -1827,98 +1823,6 @@
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#define SRACK 0x10 /* Self-refresh acknowledge */
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#define MDDRENABLE 0x20 /* Mobile DDR enable */
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/* Bit masks for EBIU_DDRBRC0 */
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#define BRC0 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBRC1 */
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#define BRC1 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBRC2 */
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#define BRC2 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBRC3 */
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#define BRC3 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBRC4 */
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#define BRC4 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBRC5 */
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#define BRC5 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBRC6 */
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#define BRC6 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBRC7 */
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#define BRC7 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBWC0 */
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#define BWC0 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBWC1 */
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#define BWC1 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBWC2 */
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#define BWC2 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBWC3 */
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#define BWC3 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBWC4 */
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#define BWC4 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBWC5 */
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#define BWC5 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBWC6 */
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#define BWC6 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRBWC7 */
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#define BWC7 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRACCT */
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#define ACCT 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRTACT */
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#define TECT 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRARCT */
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#define ARCT 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRGC0 */
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#define GC0 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRGC1 */
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#define GC1 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRGC2 */
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#define GC2 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRGC3 */
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#define GC3 0xffffffff /* Count */
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/* Bit masks for EBIU_DDRMCEN */
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#define B0WCENABLE 0x1 /* Bank 0 write count enable */
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@ -2408,14 +2312,6 @@
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#define UCCT 0x40 /* Universal Counter CAN Trigger */
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#define UCE 0x80 /* Universal Counter Enable */
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/* Bit masks for CAN0_UCCNT */
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#define UCCNT 0xffff /* Universal Counter Count Value */
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/* Bit masks for CAN0_UCRC */
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#define UCVAL 0xffff /* Universal Counter Reload/Capture Value */
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/* Bit masks for CAN0_CEC */
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#define RXECNT 0xff /* Receive Error Counter */
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