intelfb: add pll index to the intelfb structure
Add the pll index into the information structure, change get_chipset to take only the info structure, use plls in correct places
This commit is contained in:
parent
7258b11d2e
commit
d024960cff
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@ -277,6 +277,9 @@ struct intelfb_info {
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/* driver registered */
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/* driver registered */
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int registered;
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int registered;
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/* index into plls */
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int pll_index;
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};
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};
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/*** function prototypes ***/
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/*** function prototypes ***/
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@ -584,8 +584,7 @@ intelfb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
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/* Get the chipset info. */
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/* Get the chipset info. */
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dinfo->pci_chipset = pdev->device;
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dinfo->pci_chipset = pdev->device;
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if (intelfbhw_get_chipset(pdev, &dinfo->name, &dinfo->chipset,
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if (intelfbhw_get_chipset(pdev, dinfo)) {
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&dinfo->mobile)) {
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cleanup(dinfo);
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cleanup(dinfo);
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return -ENODEV;
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return -ENODEV;
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}
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}
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@ -61,67 +61,71 @@ struct pll_min_max plls[PLLS_MAX] = {
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};
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};
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int
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int
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intelfbhw_get_chipset(struct pci_dev *pdev, const char **name, int *chipset,
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intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
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int *mobile)
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{
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{
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u32 tmp;
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u32 tmp;
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if (!pdev || !dinfo)
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if (!pdev || !name || !chipset || !mobile)
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return 1;
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return 1;
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switch (pdev->device) {
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_830M:
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case PCI_DEVICE_ID_INTEL_830M:
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*name = "Intel(R) 830M";
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dinfo->name = "Intel(R) 830M";
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*chipset = INTEL_830M;
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dinfo->chipset = INTEL_830M;
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*mobile = 1;
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dinfo->mobile = 1;
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dinfo->pll_index = PLLS_I8xx;
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return 0;
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return 0;
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case PCI_DEVICE_ID_INTEL_845G:
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case PCI_DEVICE_ID_INTEL_845G:
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*name = "Intel(R) 845G";
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dinfo->name = "Intel(R) 845G";
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*chipset = INTEL_845G;
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dinfo->chipset = INTEL_845G;
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*mobile = 0;
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dinfo->mobile = 0;
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dinfo->pll_index = PLLS_I8xx;
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return 0;
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return 0;
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case PCI_DEVICE_ID_INTEL_85XGM:
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case PCI_DEVICE_ID_INTEL_85XGM:
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tmp = 0;
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tmp = 0;
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*mobile = 1;
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dinfo->mobile = 1;
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dinfo->pll_index = PLLS_I8xx;
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pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
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pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
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switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
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switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
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INTEL_85X_VARIANT_MASK) {
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INTEL_85X_VARIANT_MASK) {
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case INTEL_VAR_855GME:
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case INTEL_VAR_855GME:
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*name = "Intel(R) 855GME";
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dinfo->name = "Intel(R) 855GME";
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*chipset = INTEL_855GME;
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dinfo->chipset = INTEL_855GME;
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return 0;
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return 0;
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case INTEL_VAR_855GM:
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case INTEL_VAR_855GM:
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*name = "Intel(R) 855GM";
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dinfo->name = "Intel(R) 855GM";
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*chipset = INTEL_855GM;
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dinfo->chipset = INTEL_855GM;
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return 0;
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return 0;
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case INTEL_VAR_852GME:
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case INTEL_VAR_852GME:
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*name = "Intel(R) 852GME";
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dinfo->name = "Intel(R) 852GME";
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*chipset = INTEL_852GME;
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dinfo->chipset = INTEL_852GME;
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return 0;
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return 0;
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case INTEL_VAR_852GM:
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case INTEL_VAR_852GM:
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*name = "Intel(R) 852GM";
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dinfo->name = "Intel(R) 852GM";
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*chipset = INTEL_852GM;
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dinfo->chipset = INTEL_852GM;
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return 0;
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return 0;
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default:
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default:
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*name = "Intel(R) 852GM/855GM";
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dinfo->name = "Intel(R) 852GM/855GM";
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*chipset = INTEL_85XGM;
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dinfo->chipset = INTEL_85XGM;
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return 0;
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return 0;
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}
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}
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break;
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break;
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case PCI_DEVICE_ID_INTEL_865G:
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case PCI_DEVICE_ID_INTEL_865G:
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*name = "Intel(R) 865G";
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dinfo->name = "Intel(R) 865G";
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*chipset = INTEL_865G;
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dinfo->chipset = INTEL_865G;
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*mobile = 0;
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dinfo->mobile = 0;
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dinfo->pll_index = PLLS_I8xx;
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return 0;
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return 0;
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case PCI_DEVICE_ID_INTEL_915G:
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case PCI_DEVICE_ID_INTEL_915G:
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*name = "Intel(R) 915G";
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dinfo->name = "Intel(R) 915G";
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*chipset = INTEL_915G;
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dinfo->chipset = INTEL_915G;
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*mobile = 0;
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dinfo->mobile = 0;
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dinfo->pll_index = PLLS_I9xx;
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return 0;
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return 0;
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case PCI_DEVICE_ID_INTEL_915GM:
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case PCI_DEVICE_ID_INTEL_915GM:
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*name = "Intel(R) 915GM";
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dinfo->name = "Intel(R) 915GM";
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*chipset = INTEL_915GM;
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dinfo->chipset = INTEL_915GM;
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*mobile = 1;
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dinfo->mobile = 1;
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dinfo->pll_index = PLLS_I9xx;
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return 0;
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return 0;
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default:
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default:
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return 1;
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return 1;
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@ -549,14 +553,33 @@ intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
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}
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}
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static int calc_vclock3(int index, int m, int n, int p)
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{
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return PLL_REFCLK * m / n / p;
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}
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static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
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{
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switch(index)
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{
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case PLLS_I9xx:
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return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
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((p1)) * (p2 ? 10 : 5)));
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case PLLS_I8xx:
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default:
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return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
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((p1+2) * (1 << (p2 + 1)))));
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}
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}
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void
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void
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intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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{
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{
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#if REGDUMP
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#if REGDUMP
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int i, m1, m2, n, p1, p2;
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int i, m1, m2, n, p1, p2;
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int index = dinfo->pll_index;
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DBG_MSG("intelfbhw_print_hw_state\n");
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DBG_MSG("intelfbhw_print_hw_state\n");
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if (!hw || !dinfo)
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if (!hw || !dinfo)
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return;
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return;
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/* Read in as much of the HW state as possible. */
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/* Read in as much of the HW state as possible. */
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@ -573,9 +596,10 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
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p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
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p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
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p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
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printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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m1, m2, n, p1, p2);
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m1, m2, n, p1, p2);
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printk(" VGA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
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printk(" VGA0: clock is %d\n",
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calc_vclock(index, m1, m2, n, p1, p2));
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n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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@ -585,16 +609,16 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
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p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
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p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
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p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
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printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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m1, m2, n, p1, p2);
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m1, m2, n, p1, p2);
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printk(" VGA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
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printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
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printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
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printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
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printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
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printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
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printk(" FPA0: 0x%08x\n", hw->fpa0);
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printk(" FPA0: 0x%08x\n", hw->fpa0);
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printk(" FPA1: 0x%08x\n", hw->fpa1);
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printk(" FPA1: 0x%08x\n", hw->fpa1);
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printk(" FPB0: 0x%08x\n", hw->fpb0);
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printk(" FPB0: 0x%08x\n", hw->fpb0);
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printk(" FPB1: 0x%08x\n", hw->fpb1);
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printk(" FPB1: 0x%08x\n", hw->fpb1);
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n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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@ -604,9 +628,9 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
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p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
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p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
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p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
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printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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m1, m2, n, p1, p2);
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m1, m2, n, p1, p2);
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printk(" PLLA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
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printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
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n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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@ -616,16 +640,16 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
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p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
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p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
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p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
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printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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m1, m2, n, p1, p2);
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m1, m2, n, p1, p2);
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printk(" PLLA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
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printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
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#if 0
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#if 0
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printk(" PALETTE_A:\n");
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printk(" PALETTE_A:\n");
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for (i = 0; i < PALETTE_8_ENTRIES)
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for (i = 0; i < PALETTE_8_ENTRIES)
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printk(" %3d: 0x%08x\n", i, hw->palette_a[i];
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printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
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printk(" PALETTE_B:\n");
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printk(" PALETTE_B:\n");
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for (i = 0; i < PALETTE_8_ENTRIES)
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for (i = 0; i < PALETTE_8_ENTRIES)
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printk(" %3d: 0x%08x\n", i, hw->palette_b[i];
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printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
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#endif
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#endif
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printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
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printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
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@ -700,12 +724,12 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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}
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}
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for (i = 0; i < 3; i++) {
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for (i = 0; i < 3; i++) {
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printk(" SWF3%d 0x%08x\n", i,
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printk(" SWF3%d 0x%08x\n", i,
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hw->swf3x[i]);
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hw->swf3x[i]);
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}
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}
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for (i = 0; i < 8; i++)
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for (i = 0; i < 8; i++)
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printk(" FENCE%d 0x%08x\n", i,
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printk(" FENCE%d 0x%08x\n", i,
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hw->fence[i]);
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hw->fence[i]);
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printk(" INSTPM 0x%08x\n", hw->instpm);
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printk(" INSTPM 0x%08x\n", hw->instpm);
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printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
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printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
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printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
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printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
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@ -715,6 +739,8 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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#endif
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#endif
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}
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}
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/* Split the M parameter into M1 and M2. */
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/* Split the M parameter into M1 and M2. */
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static int
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static int
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splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
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splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
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@ -742,7 +768,17 @@ splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
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{
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{
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int p1, p2;
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int p1, p2;
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if (index==PLLS_I8xx)
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if (index == PLLS_I9xx)
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{
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p1 = (p / 10) + 1;
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p2 = 0;
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*retp1 = (unsigned int)p1;
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*retp2 = (unsigned int)p2;
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return 0;
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}
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if (index == PLLS_I8xx)
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{
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{
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if (p % 4 == 0)
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if (p % 4 == 0)
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p2 = 1;
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p2 = 1;
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@ -812,7 +848,7 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
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m = plls[index].min_m;
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m = plls[index].min_m;
|
||||||
if (m > plls[index].max_m)
|
if (m > plls[index].max_m)
|
||||||
m = plls[index].max_m;
|
m = plls[index].max_m;
|
||||||
f_out = CALC_VCLOCK3(m, n, p);
|
f_out = calc_vclock3(index, m, n, p);
|
||||||
if (splitm(index, m, &m1, &m2)) {
|
if (splitm(index, m, &m1, &m2)) {
|
||||||
WRN_MSG("cannot split m = %d\n", m);
|
WRN_MSG("cannot split m = %d\n", m);
|
||||||
n++;
|
n++;
|
||||||
|
@ -849,14 +885,15 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
|
||||||
DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
|
DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
|
||||||
"f: %d (%d), VCO: %d\n",
|
"f: %d (%d), VCO: %d\n",
|
||||||
m, m1, m2, n, n1, p, p1, p2,
|
m, m1, m2, n, n1, p, p1, p2,
|
||||||
CALC_VCLOCK3(m, n, p), CALC_VCLOCK(m1, m2, n1, p1, p2),
|
calc_vclock3(index, m, n, p),
|
||||||
CALC_VCLOCK3(m, n, p) * p);
|
calc_vclock(index, m1, m2, n1, p1, p2),
|
||||||
|
calc_vclock3(index, m, n, p) * p);
|
||||||
*retm1 = m1;
|
*retm1 = m1;
|
||||||
*retm2 = m2;
|
*retm2 = m2;
|
||||||
*retn = n1;
|
*retn = n1;
|
||||||
*retp1 = p1;
|
*retp1 = p1;
|
||||||
*retp2 = p2;
|
*retp2 = p2;
|
||||||
*retclock = CALC_VCLOCK(m1, m2, n1, p1, p2);
|
*retclock = calc_vclock(index, m1, m2, n1, p1, p2);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -953,7 +990,7 @@ intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
|
||||||
/* Desired clock in kHz */
|
/* Desired clock in kHz */
|
||||||
clock_target = 1000000000 / var->pixclock;
|
clock_target = 1000000000 / var->pixclock;
|
||||||
|
|
||||||
if (calc_pll_params(PLLS_I8xx, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
|
if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
|
||||||
WRN_MSG("calc_pll_params failed\n");
|
WRN_MSG("calc_pll_params failed\n");
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
|
@ -158,12 +158,6 @@
|
||||||
#define MIN_CLOCK 25000
|
#define MIN_CLOCK 25000
|
||||||
#define MAX_CLOCK 350000
|
#define MAX_CLOCK 350000
|
||||||
|
|
||||||
#define CALC_VCLOCK(m1, m2, n, p1, p2) \
|
|
||||||
((PLL_REFCLK * (5 * ((m1) + 2) + ((m2) + 2)) / ((n) + 2)) / \
|
|
||||||
(((p1) + 2) * (1 << (p2 + 1))))
|
|
||||||
|
|
||||||
#define CALC_VCLOCK3(m, n, p) ((PLL_REFCLK * (m) / (n)) / (p))
|
|
||||||
|
|
||||||
/* Two pipes */
|
/* Two pipes */
|
||||||
#define PIPE_A 0
|
#define PIPE_A 0
|
||||||
#define PIPE_B 1
|
#define PIPE_B 1
|
||||||
|
@ -507,8 +501,7 @@
|
||||||
|
|
||||||
|
|
||||||
/* function protoypes */
|
/* function protoypes */
|
||||||
extern int intelfbhw_get_chipset(struct pci_dev *pdev, const char **name,
|
extern int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo);
|
||||||
int *chipset, int *mobile);
|
|
||||||
extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
|
extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
|
||||||
int *stolen_size);
|
int *stolen_size);
|
||||||
extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo);
|
extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo);
|
||||||
|
|
Loading…
Reference in a new issue