ARM: at91/PMC: fix at91sam9n12 USB FS init
at91sam9n12 has Full-speed only USB. So we should add it to the list in at91_pllb_usbfs_clock_init() function. Moreover, at91sam9n12 has an unusual PMC in the sense that it has a PLLB but also has a USB clock register. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Tested-by: Bo Shen <voice.shen@atmel.com>
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@ -489,7 +489,7 @@ static int at91_clk_show(struct seq_file *s, void *unused)
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seq_printf(s, "UCKR = %8x\n", uckr);
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seq_printf(s, "UCKR = %8x\n", uckr);
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}
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}
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seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
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seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
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if (cpu_has_upll())
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if (cpu_has_upll() || cpu_is_at91sam9n12())
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seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
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seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
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seq_printf(s, "SR = %8x\n", sr);
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seq_printf(s, "SR = %8x\n", sr);
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@ -614,6 +614,8 @@ static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
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{
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{
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if (pll == &pllb && (reg & AT91_PMC_USB96M))
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if (pll == &pllb && (reg & AT91_PMC_USB96M))
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return freq / 2;
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return freq / 2;
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else if (pll == &utmi_clk || cpu_is_at91sam9n12())
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return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
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else
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else
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return freq;
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return freq;
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}
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}
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@ -683,6 +685,8 @@ static struct clk *const standard_pmc_clocks[] __initconst = {
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/* PLLB generated USB full speed clock init */
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/* PLLB generated USB full speed clock init */
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static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
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static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
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{
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{
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unsigned int reg;
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/*
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/*
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* USB clock init: choose 48 MHz PLLB value,
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* USB clock init: choose 48 MHz PLLB value,
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* disable 48MHz clock during usb peripheral suspend.
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* disable 48MHz clock during usb peripheral suspend.
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@ -691,22 +695,35 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
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*/
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*/
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uhpck.parent = &pllb;
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uhpck.parent = &pllb;
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at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
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reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
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pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
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pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
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if (cpu_is_at91rm9200()) {
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if (cpu_is_at91rm9200()) {
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reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
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uhpck.pmc_mask = AT91RM9200_PMC_UHP;
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uhpck.pmc_mask = AT91RM9200_PMC_UHP;
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udpck.pmc_mask = AT91RM9200_PMC_UDP;
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udpck.pmc_mask = AT91RM9200_PMC_UDP;
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at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
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at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
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} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
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} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
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cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
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cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
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cpu_is_at91sam9g10()) {
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cpu_is_at91sam9g10()) {
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reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
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uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
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udpck.pmc_mask = AT91SAM926x_PMC_UDP;
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} else if (cpu_is_at91sam9n12()) {
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/* Divider for USB clock is in USB clock register for 9n12 */
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reg = AT91_PMC_USBS_PLLB;
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/* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
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reg |= AT91_PMC_OHCIUSBDIV_2;
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at91_pmc_write(AT91_PMC_USB, reg);
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/* Still setup masks */
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uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
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uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
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udpck.pmc_mask = AT91SAM926x_PMC_UDP;
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udpck.pmc_mask = AT91SAM926x_PMC_UDP;
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}
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}
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at91_pmc_write(AT91_CKGR_PLLBR, 0);
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at91_pmc_write(AT91_CKGR_PLLBR, 0);
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udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
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udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
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uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
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uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
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}
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}
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/* UPLL generated USB full speed clock init */
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/* UPLL generated USB full speed clock init */
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@ -130,7 +130,10 @@ extern void __iomem *at91_pmc_base;
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#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
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#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
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#define AT91_PMC_USBS_PLLA (0 << 0)
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#define AT91_PMC_USBS_PLLA (0 << 0)
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#define AT91_PMC_USBS_UPLL (1 << 0)
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#define AT91_PMC_USBS_UPLL (1 << 0)
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#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */
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#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
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#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
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#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8)
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#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8)
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#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
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#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
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#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
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#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
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