iommu: io-pgtable: Add ARM Mali midgard MMU page table format
ARM Mali midgard GPU is similar to standard 64-bit stage 1 page tables, but have a few differences. Add a new format type to represent the format. The input address size is 48-bits and the output address size is 40-bits (and possibly less?). Note that the later bifrost GPUs follow the standard 64-bit stage 1 format. The differences in the format compared to 64-bit stage 1 format are: The 3rd level page entry bits are 0x1 instead of 0x3 for page entries. The access flags are not read-only and unprivileged, but read and write. This is similar to stage 2 entries, but the memory attributes field matches stage 1 being an index. The nG bit is not set by the vendor driver. This one didn't seem to matter, but we'll keep it aligned to the vendor driver. Cc: Will Deacon <will.deacon@arm.com> Acked-by: Robin Murphy <robin.murphy@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: iommu@lists.linux-foundation.org Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190409205427.6943-2-robh@kernel.orghifive-unleashed-5.2
Rob Herring
parent
0eb2766dd6
commit
d08d42de64
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@ -172,6 +172,10 @@
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#define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
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#define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
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#define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0)
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#define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2)
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#define ARM_MALI_LPAE_TTBR_SHARE_OUTER BIT(4)
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/* IOPTE accessors */
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#define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
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@ -180,11 +184,6 @@
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#define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
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#define iopte_leaf(pte,l) \
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(l == (ARM_LPAE_MAX_LEVELS - 1) ? \
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(iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_PAGE) : \
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(iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_BLOCK))
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struct arm_lpae_io_pgtable {
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struct io_pgtable iop;
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@ -198,6 +197,15 @@ struct arm_lpae_io_pgtable {
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typedef u64 arm_lpae_iopte;
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static inline bool iopte_leaf(arm_lpae_iopte pte, int lvl,
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enum io_pgtable_fmt fmt)
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{
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if (lvl == (ARM_LPAE_MAX_LEVELS - 1) && fmt != ARM_MALI_LPAE)
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return iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_PAGE;
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return iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_BLOCK;
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}
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static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr,
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struct arm_lpae_io_pgtable *data)
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{
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@ -303,12 +311,14 @@ static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
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if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS)
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pte |= ARM_LPAE_PTE_NS;
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if (lvl == ARM_LPAE_MAX_LEVELS - 1)
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if (data->iop.fmt != ARM_MALI_LPAE && lvl == ARM_LPAE_MAX_LEVELS - 1)
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pte |= ARM_LPAE_PTE_TYPE_PAGE;
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else
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pte |= ARM_LPAE_PTE_TYPE_BLOCK;
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pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS;
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if (data->iop.fmt != ARM_MALI_LPAE)
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pte |= ARM_LPAE_PTE_AF;
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pte |= ARM_LPAE_PTE_SH_IS;
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pte |= paddr_to_iopte(paddr, data);
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__arm_lpae_set_pte(ptep, pte, &data->iop.cfg);
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@ -321,7 +331,7 @@ static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
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{
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arm_lpae_iopte pte = *ptep;
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if (iopte_leaf(pte, lvl)) {
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if (iopte_leaf(pte, lvl, data->iop.fmt)) {
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/* We require an unmap first */
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WARN_ON(!selftest_running);
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return -EEXIST;
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@ -409,7 +419,7 @@ static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
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__arm_lpae_sync_pte(ptep, cfg);
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}
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if (pte && !iopte_leaf(pte, lvl)) {
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if (pte && !iopte_leaf(pte, lvl, data->iop.fmt)) {
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cptep = iopte_deref(pte, data);
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} else if (pte) {
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/* We require an unmap first */
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@ -429,31 +439,37 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
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if (data->iop.fmt == ARM_64_LPAE_S1 ||
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data->iop.fmt == ARM_32_LPAE_S1) {
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pte = ARM_LPAE_PTE_nG;
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if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
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pte |= ARM_LPAE_PTE_AP_RDONLY;
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if (!(prot & IOMMU_PRIV))
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pte |= ARM_LPAE_PTE_AP_UNPRIV;
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if (prot & IOMMU_MMIO)
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pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
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<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
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else if (prot & IOMMU_CACHE)
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pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
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<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
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} else {
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pte = ARM_LPAE_PTE_HAP_FAULT;
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if (prot & IOMMU_READ)
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pte |= ARM_LPAE_PTE_HAP_READ;
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if (prot & IOMMU_WRITE)
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pte |= ARM_LPAE_PTE_HAP_WRITE;
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}
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/*
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* Note that this logic is structured to accommodate Mali LPAE
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* having stage-1-like attributes but stage-2-like permissions.
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*/
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if (data->iop.fmt == ARM_64_LPAE_S2 ||
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data->iop.fmt == ARM_32_LPAE_S2) {
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if (prot & IOMMU_MMIO)
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pte |= ARM_LPAE_PTE_MEMATTR_DEV;
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else if (prot & IOMMU_CACHE)
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pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
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else
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pte |= ARM_LPAE_PTE_MEMATTR_NC;
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} else {
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if (prot & IOMMU_MMIO)
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pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
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<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
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else if (prot & IOMMU_CACHE)
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pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
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<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
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}
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if (prot & IOMMU_NOEXEC)
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@ -511,7 +527,7 @@ static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
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while (ptep != end) {
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arm_lpae_iopte pte = *ptep++;
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if (!pte || iopte_leaf(pte, lvl))
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if (!pte || iopte_leaf(pte, lvl, data->iop.fmt))
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continue;
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__arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
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@ -602,7 +618,7 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
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if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) {
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__arm_lpae_set_pte(ptep, 0, &iop->cfg);
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if (!iopte_leaf(pte, lvl)) {
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if (!iopte_leaf(pte, lvl, iop->fmt)) {
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/* Also flush any partial walks */
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io_pgtable_tlb_add_flush(iop, iova, size,
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ARM_LPAE_GRANULE(data), false);
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@ -621,7 +637,7 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
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}
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return size;
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} else if (iopte_leaf(pte, lvl)) {
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} else if (iopte_leaf(pte, lvl, iop->fmt)) {
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/*
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* Insert a table at the next level to map the old region,
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* minus the part we want to unmap
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@ -669,7 +685,7 @@ static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
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return 0;
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/* Leaf entry? */
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if (iopte_leaf(pte,lvl))
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if (iopte_leaf(pte, lvl, data->iop.fmt))
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goto found_translation;
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/* Take it to the next level */
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@ -995,6 +1011,32 @@ arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
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return iop;
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}
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static struct io_pgtable *
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arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
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{
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struct io_pgtable *iop;
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if (cfg->ias != 48 || cfg->oas > 40)
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return NULL;
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cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
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iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
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if (iop) {
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u64 mair, ttbr;
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/* Copy values as union fields overlap */
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mair = cfg->arm_lpae_s1_cfg.mair[0];
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ttbr = cfg->arm_lpae_s1_cfg.ttbr[0];
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cfg->arm_mali_lpae_cfg.memattr = mair;
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cfg->arm_mali_lpae_cfg.transtab = ttbr |
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ARM_MALI_LPAE_TTBR_READ_INNER |
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ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
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}
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return iop;
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}
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struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
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.alloc = arm_64_lpae_alloc_pgtable_s1,
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.free = arm_lpae_free_pgtable,
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@ -1015,6 +1057,11 @@ struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {
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.free = arm_lpae_free_pgtable,
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};
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struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns = {
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.alloc = arm_mali_lpae_alloc_pgtable,
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.free = arm_lpae_free_pgtable,
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};
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#ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST
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static struct io_pgtable_cfg *cfg_cookie;
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@ -30,6 +30,7 @@ io_pgtable_init_table[IO_PGTABLE_NUM_FMTS] = {
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[ARM_32_LPAE_S2] = &io_pgtable_arm_32_lpae_s2_init_fns,
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[ARM_64_LPAE_S1] = &io_pgtable_arm_64_lpae_s1_init_fns,
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[ARM_64_LPAE_S2] = &io_pgtable_arm_64_lpae_s2_init_fns,
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[ARM_MALI_LPAE] = &io_pgtable_arm_mali_lpae_init_fns,
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#endif
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#ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S
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[ARM_V7S] = &io_pgtable_arm_v7s_init_fns,
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@ -12,6 +12,7 @@ enum io_pgtable_fmt {
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ARM_64_LPAE_S1,
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ARM_64_LPAE_S2,
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ARM_V7S,
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ARM_MALI_LPAE,
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IO_PGTABLE_NUM_FMTS,
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};
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@ -108,6 +109,11 @@ struct io_pgtable_cfg {
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u32 nmrr;
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u32 prrr;
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} arm_v7s_cfg;
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struct {
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u64 transtab;
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u64 memattr;
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} arm_mali_lpae_cfg;
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};
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};
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@ -209,5 +215,6 @@ extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns;
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#endif /* __IO_PGTABLE_H */
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