iommu/exynos: Refactor fault handling code
This patch provides a new implementation for page fault handing code. The new implementation is ready for future extensions. No functional changes have been made. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>hifive-unleashed-5.1
Marek Szyprowski
Joerg Roedel
parent
02cdc365cf
commit
d093fc7e83
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@ -148,40 +148,25 @@ static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
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lv2table_base(sent)) + lv2ent_offset(iova);
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}
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enum exynos_sysmmu_inttype {
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SYSMMU_PAGEFAULT,
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SYSMMU_AR_MULTIHIT,
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SYSMMU_AW_MULTIHIT,
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SYSMMU_BUSERROR,
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SYSMMU_AR_SECURITY,
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SYSMMU_AR_ACCESS,
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SYSMMU_AW_SECURITY,
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SYSMMU_AW_PROTECTION, /* 7 */
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SYSMMU_FAULT_UNKNOWN,
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SYSMMU_FAULTS_NUM
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/*
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* IOMMU fault information register
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*/
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struct sysmmu_fault_info {
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unsigned int bit; /* bit number in STATUS register */
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unsigned short addr_reg; /* register to read VA fault address */
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const char *name; /* human readable fault name */
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unsigned int type; /* fault type for report_iommu_fault */
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};
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static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
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REG_PAGE_FAULT_ADDR,
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REG_AR_FAULT_ADDR,
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REG_AW_FAULT_ADDR,
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REG_DEFAULT_SLAVE_ADDR,
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REG_AR_FAULT_ADDR,
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REG_AR_FAULT_ADDR,
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REG_AW_FAULT_ADDR,
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REG_AW_FAULT_ADDR
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};
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static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
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"PAGE FAULT",
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"AR MULTI-HIT FAULT",
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"AW MULTI-HIT FAULT",
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"BUS ERROR",
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"AR SECURITY PROTECTION FAULT",
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"AR ACCESS PROTECTION FAULT",
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"AW SECURITY PROTECTION FAULT",
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"AW ACCESS PROTECTION FAULT",
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"UNKNOWN FAULT"
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static const struct sysmmu_fault_info sysmmu_faults[] = {
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{ 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
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{ 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
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{ 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
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{ 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
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{ 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
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{ 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
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{ 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
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{ 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
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};
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/*
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@ -299,24 +284,19 @@ static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
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__sysmmu_tlb_invalidate(data);
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}
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static void show_fault_information(const char *name,
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enum exynos_sysmmu_inttype itype,
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phys_addr_t pgtable_base, sysmmu_iova_t fault_addr)
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static void show_fault_information(struct sysmmu_drvdata *data,
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const struct sysmmu_fault_info *finfo,
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sysmmu_iova_t fault_addr)
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{
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sysmmu_pte_t *ent;
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if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
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itype = SYSMMU_FAULT_UNKNOWN;
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pr_err("%s occurred at %#x by %s(Page table base: %pa)\n",
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sysmmu_fault_name[itype], fault_addr, name, &pgtable_base);
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ent = section_entry(phys_to_virt(pgtable_base), fault_addr);
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pr_err("\tLv1 entry: %#x\n", *ent);
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dev_err(data->sysmmu, "%s FAULT occurred at %#x (page table base: %pa)\n",
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finfo->name, fault_addr, &data->pgtable);
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ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
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dev_err(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
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if (lv1ent_page(ent)) {
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ent = page_entry(ent, fault_addr);
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pr_err("\t Lv2 entry: %#x\n", *ent);
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dev_err(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
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}
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}
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@ -324,8 +304,10 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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{
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/* SYSMMU is in blocked state when interrupt occurred. */
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struct sysmmu_drvdata *data = dev_id;
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enum exynos_sysmmu_inttype itype;
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sysmmu_iova_t addr = -1;
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const struct sysmmu_fault_info *finfo = sysmmu_faults;
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int i, n = ARRAY_SIZE(sysmmu_faults);
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unsigned int itype;
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sysmmu_iova_t fault_addr = -1;
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int ret = -ENOSYS;
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WARN_ON(!is_sysmmu_active(data));
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@ -334,29 +316,20 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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clk_enable(data->clk_master);
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itype = (enum exynos_sysmmu_inttype)
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__ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
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if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
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itype = SYSMMU_FAULT_UNKNOWN;
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else
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addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]);
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itype = __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
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for (i = 0; i < n; i++, finfo++)
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if (finfo->bit == itype)
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break;
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/* unknown/unsupported fault */
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BUG_ON(i == n);
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if (itype == SYSMMU_FAULT_UNKNOWN) {
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pr_err("%s: Fault is not occurred by System MMU '%s'!\n",
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__func__, dev_name(data->sysmmu));
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pr_err("%s: Please check if IRQ is correctly configured.\n",
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__func__);
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BUG();
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} else {
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unsigned int base =
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__raw_readl(data->sfrbase + REG_PT_BASE_ADDR);
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show_fault_information(dev_name(data->sysmmu),
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itype, base, addr);
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if (data->domain)
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ret = report_iommu_fault(&data->domain->domain,
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data->master, addr, itype);
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}
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/* print debug message */
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fault_addr = __raw_readl(data->sfrbase + finfo->addr_reg);
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show_fault_information(data, finfo, fault_addr);
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if (data->domain)
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ret = report_iommu_fault(&data->domain->domain,
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data->master, fault_addr, finfo->type);
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/* fault is not recovered by fault handler */
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BUG_ON(ret != 0);
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