drm/radeon: fill in gpu init for Oland
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1127,7 +1127,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
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}
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}
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WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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}
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}
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} else if (rdev->family == CHIP_VERDE) {
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} else if ((rdev->family == CHIP_VERDE) ||
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(rdev->family == CHIP_OLAND)) {
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for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
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for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
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switch (reg_offset) {
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switch (reg_offset) {
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case 0: /* non-AA compressed depth or any compressed stencil */
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case 0: /* non-AA compressed depth or any compressed stencil */
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@ -1566,6 +1567,23 @@ static void si_gpu_init(struct radeon_device *rdev)
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rdev->config.si.max_gs_threads = 32;
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rdev->config.si.max_gs_threads = 32;
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rdev->config.si.max_hw_contexts = 8;
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rdev->config.si.max_hw_contexts = 8;
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rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
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rdev->config.si.sc_prim_fifo_size_backend = 0x40;
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rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
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rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
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gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
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break;
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case CHIP_OLAND:
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rdev->config.si.max_shader_engines = 1;
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rdev->config.si.max_tile_pipes = 4;
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rdev->config.si.max_cu_per_sh = 6;
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rdev->config.si.max_sh_per_se = 1;
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rdev->config.si.max_backends_per_se = 2;
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rdev->config.si.max_texture_channel_caches = 4;
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rdev->config.si.max_gprs = 256;
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rdev->config.si.max_gs_threads = 16;
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rdev->config.si.max_hw_contexts = 8;
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rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
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rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
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rdev->config.si.sc_prim_fifo_size_backend = 0x40;
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rdev->config.si.sc_prim_fifo_size_backend = 0x40;
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rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
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rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
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