drm/i915/skl: Implement WaDisablePowerCompilerClockGating
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -5256,8 +5256,9 @@ enum skl_disp_power_wells {
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#define COMMON_SLICE_CHICKEN2 0x7014
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# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
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#define HIZ_CHICKEN 0x7018
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# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
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#define HIZ_CHICKEN 0x7018
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# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
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# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
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#define GEN9_SLICE_COMMON_ECO_CHICKEN0 0x7308
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#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
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@ -1004,8 +1004,16 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
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static int skl_init_workarounds(struct intel_engine_cs *ring)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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gen9_init_workarounds(ring);
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/* WaDisablePowerCompilerClockGating:skl */
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if (INTEL_REVID(dev) == SKL_REVID_B0)
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WA_SET_BIT_MASKED(HIZ_CHICKEN,
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BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
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return 0;
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}
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