mfd: Add new driver for MAX77650 PMIC
Add the core MFD driver for max77650 PMIC. We define five sub-devices for which the drivers will be added in subsequent patches. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>hifive-unleashed-5.2
Bartosz Golaszewski
Lee Jones
parent
1946f9967c
commit
d0f6033450
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@ -733,6 +733,20 @@ config MFD_MAX77620
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provides common support for accessing the device; additional drivers
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must be enabled in order to use the functionality of the device.
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config MFD_MAX77650
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tristate "Maxim MAX77650/77651 PMIC Support"
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depends on I2C
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depends on OF || COMPILE_TEST
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select MFD_CORE
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select REGMAP_I2C
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help
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Say Y here to add support for Maxim Semiconductor MAX77650 and
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MAX77651 Power Management ICs. This is the core multifunction
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driver for interacting with the device. The module name is
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'max77650'. Additional drivers can be enabled in order to use
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the following functionalities of the device: GPIO, regulator,
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charger, LED, onkey.
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config MFD_MAX77686
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tristate "Maxim Semiconductor MAX77686/802 PMIC Support"
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depends on I2C
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@ -155,6 +155,7 @@ obj-$(CONFIG_MFD_DA9150) += da9150-core.o
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obj-$(CONFIG_MFD_MAX14577) += max14577.o
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obj-$(CONFIG_MFD_MAX77620) += max77620.o
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obj-$(CONFIG_MFD_MAX77650) += max77650.o
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obj-$(CONFIG_MFD_MAX77686) += max77686.o
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obj-$(CONFIG_MFD_MAX77693) += max77693.o
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obj-$(CONFIG_MFD_MAX77843) += max77843.o
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@ -0,0 +1,232 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2018 BayLibre SAS
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// Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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//
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// Core MFD driver for MAXIM 77650/77651 charger/power-supply.
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// Programming manual: https://pdfserv.maximintegrated.com/en/an/AN6428.pdf
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/max77650.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#define MAX77650_INT_GPI_F_MSK BIT(0)
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#define MAX77650_INT_GPI_R_MSK BIT(1)
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#define MAX77650_INT_GPI_MSK \
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(MAX77650_INT_GPI_F_MSK | MAX77650_INT_GPI_R_MSK)
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#define MAX77650_INT_nEN_F_MSK BIT(2)
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#define MAX77650_INT_nEN_R_MSK BIT(3)
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#define MAX77650_INT_TJAL1_R_MSK BIT(4)
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#define MAX77650_INT_TJAL2_R_MSK BIT(5)
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#define MAX77650_INT_DOD_R_MSK BIT(6)
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#define MAX77650_INT_THM_MSK BIT(0)
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#define MAX77650_INT_CHG_MSK BIT(1)
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#define MAX77650_INT_CHGIN_MSK BIT(2)
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#define MAX77650_INT_TJ_REG_MSK BIT(3)
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#define MAX77650_INT_CHGIN_CTRL_MSK BIT(4)
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#define MAX77650_INT_SYS_CTRL_MSK BIT(5)
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#define MAX77650_INT_SYS_CNFG_MSK BIT(6)
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#define MAX77650_INT_GLBL_OFFSET 0
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#define MAX77650_INT_CHG_OFFSET 1
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#define MAX77650_SBIA_LPM_MASK BIT(5)
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#define MAX77650_SBIA_LPM_DISABLED 0x00
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enum {
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MAX77650_INT_GPI,
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MAX77650_INT_nEN_F,
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MAX77650_INT_nEN_R,
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MAX77650_INT_TJAL1_R,
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MAX77650_INT_TJAL2_R,
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MAX77650_INT_DOD_R,
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MAX77650_INT_THM,
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MAX77650_INT_CHG,
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MAX77650_INT_CHGIN,
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MAX77650_INT_TJ_REG,
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MAX77650_INT_CHGIN_CTRL,
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MAX77650_INT_SYS_CTRL,
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MAX77650_INT_SYS_CNFG,
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};
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static const struct resource max77650_charger_resources[] = {
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DEFINE_RES_IRQ_NAMED(MAX77650_INT_CHG, "CHG"),
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DEFINE_RES_IRQ_NAMED(MAX77650_INT_CHGIN, "CHGIN"),
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};
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static const struct resource max77650_gpio_resources[] = {
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DEFINE_RES_IRQ_NAMED(MAX77650_INT_GPI, "GPI"),
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};
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static const struct resource max77650_onkey_resources[] = {
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DEFINE_RES_IRQ_NAMED(MAX77650_INT_nEN_F, "nEN_F"),
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DEFINE_RES_IRQ_NAMED(MAX77650_INT_nEN_R, "nEN_R"),
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};
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static const struct mfd_cell max77650_cells[] = {
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{
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.name = "max77650-regulator",
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.of_compatible = "maxim,max77650-regulator",
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}, {
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.name = "max77650-charger",
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.of_compatible = "maxim,max77650-charger",
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.resources = max77650_charger_resources,
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.num_resources = ARRAY_SIZE(max77650_charger_resources),
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}, {
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.name = "max77650-gpio",
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.of_compatible = "maxim,max77650-gpio",
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.resources = max77650_gpio_resources,
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.num_resources = ARRAY_SIZE(max77650_gpio_resources),
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}, {
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.name = "max77650-led",
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.of_compatible = "maxim,max77650-led",
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}, {
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.name = "max77650-onkey",
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.of_compatible = "maxim,max77650-onkey",
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.resources = max77650_onkey_resources,
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.num_resources = ARRAY_SIZE(max77650_onkey_resources),
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},
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};
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static const struct regmap_irq max77650_irqs[] = {
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[MAX77650_INT_GPI] = {
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.reg_offset = MAX77650_INT_GLBL_OFFSET,
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.mask = MAX77650_INT_GPI_MSK,
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.type = {
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.type_falling_val = MAX77650_INT_GPI_F_MSK,
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.type_rising_val = MAX77650_INT_GPI_R_MSK,
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.types_supported = IRQ_TYPE_EDGE_BOTH,
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},
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},
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REGMAP_IRQ_REG(MAX77650_INT_nEN_F,
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MAX77650_INT_GLBL_OFFSET, MAX77650_INT_nEN_F_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_nEN_R,
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MAX77650_INT_GLBL_OFFSET, MAX77650_INT_nEN_R_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_TJAL1_R,
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MAX77650_INT_GLBL_OFFSET, MAX77650_INT_TJAL1_R_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_TJAL2_R,
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MAX77650_INT_GLBL_OFFSET, MAX77650_INT_TJAL2_R_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_DOD_R,
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MAX77650_INT_GLBL_OFFSET, MAX77650_INT_DOD_R_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_THM,
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MAX77650_INT_CHG_OFFSET, MAX77650_INT_THM_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_CHG,
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MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHG_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_CHGIN,
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MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHGIN_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_TJ_REG,
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MAX77650_INT_CHG_OFFSET, MAX77650_INT_TJ_REG_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_CHGIN_CTRL,
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MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHGIN_CTRL_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_SYS_CTRL,
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MAX77650_INT_CHG_OFFSET, MAX77650_INT_SYS_CTRL_MSK),
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REGMAP_IRQ_REG(MAX77650_INT_SYS_CNFG,
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MAX77650_INT_CHG_OFFSET, MAX77650_INT_SYS_CNFG_MSK),
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};
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static const struct regmap_irq_chip max77650_irq_chip = {
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.name = "max77650-irq",
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.irqs = max77650_irqs,
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.num_irqs = ARRAY_SIZE(max77650_irqs),
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.num_regs = 2,
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.status_base = MAX77650_REG_INT_GLBL,
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.mask_base = MAX77650_REG_INTM_GLBL,
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.type_in_mask = true,
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.type_invert = true,
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.init_ack_masked = true,
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.clear_on_unmask = true,
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};
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static const struct regmap_config max77650_regmap_config = {
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.name = "max77650",
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.reg_bits = 8,
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.val_bits = 8,
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};
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static int max77650_i2c_probe(struct i2c_client *i2c)
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{
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struct regmap_irq_chip_data *irq_data;
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struct device *dev = &i2c->dev;
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struct irq_domain *domain;
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struct regmap *map;
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unsigned int val;
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int rv, id;
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map = devm_regmap_init_i2c(i2c, &max77650_regmap_config);
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if (IS_ERR(map)) {
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dev_err(dev, "Unable to initialise I2C Regmap\n");
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return PTR_ERR(map);
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}
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rv = regmap_read(map, MAX77650_REG_CID, &val);
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if (rv) {
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dev_err(dev, "Unable to read Chip ID\n");
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return rv;
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}
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id = MAX77650_CID_BITS(val);
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switch (id) {
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case MAX77650_CID_77650A:
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case MAX77650_CID_77650C:
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case MAX77650_CID_77651A:
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case MAX77650_CID_77651B:
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break;
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default:
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dev_err(dev, "Chip not supported - ID: 0x%02x\n", id);
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return -ENODEV;
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}
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/*
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* This IC has a low-power mode which reduces the quiescent current
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* consumption to ~5.6uA but is only suitable for systems consuming
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* less than ~2mA. Since this is not likely the case even on
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* linux-based wearables - keep the chip in normal power mode.
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*/
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rv = regmap_update_bits(map,
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MAX77650_REG_CNFG_GLBL,
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MAX77650_SBIA_LPM_MASK,
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MAX77650_SBIA_LPM_DISABLED);
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if (rv) {
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dev_err(dev, "Unable to change the power mode\n");
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return rv;
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}
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rv = devm_regmap_add_irq_chip(dev, map, i2c->irq,
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IRQF_ONESHOT | IRQF_SHARED, 0,
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&max77650_irq_chip, &irq_data);
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if (rv) {
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dev_err(dev, "Unable to add Regmap IRQ chip\n");
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return rv;
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}
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domain = regmap_irq_get_domain(irq_data);
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return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
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max77650_cells, ARRAY_SIZE(max77650_cells),
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NULL, 0, domain);
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}
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static const struct of_device_id max77650_of_match[] = {
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{ .compatible = "maxim,max77650" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, max77650_of_match);
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static struct i2c_driver max77650_i2c_driver = {
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.driver = {
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.name = "max77650",
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.of_match_table = of_match_ptr(max77650_of_match),
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},
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.probe_new = max77650_i2c_probe,
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};
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module_i2c_driver(max77650_i2c_driver);
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MODULE_DESCRIPTION("MAXIM 77650/77651 multi-function core driver");
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MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,59 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 BayLibre SAS
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* Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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*
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* Common definitions for MAXIM 77650/77651 charger/power-supply.
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*/
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#ifndef MAX77650_H
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#define MAX77650_H
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#include <linux/bits.h>
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#define MAX77650_REG_INT_GLBL 0x00
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#define MAX77650_REG_INT_CHG 0x01
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#define MAX77650_REG_STAT_CHG_A 0x02
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#define MAX77650_REG_STAT_CHG_B 0x03
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#define MAX77650_REG_ERCFLAG 0x04
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#define MAX77650_REG_STAT_GLBL 0x05
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#define MAX77650_REG_INTM_GLBL 0x06
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#define MAX77650_REG_INTM_CHG 0x07
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#define MAX77650_REG_CNFG_GLBL 0x10
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#define MAX77650_REG_CID 0x11
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#define MAX77650_REG_CNFG_GPIO 0x12
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#define MAX77650_REG_CNFG_CHG_A 0x18
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#define MAX77650_REG_CNFG_CHG_B 0x19
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#define MAX77650_REG_CNFG_CHG_C 0x1a
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#define MAX77650_REG_CNFG_CHG_D 0x1b
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#define MAX77650_REG_CNFG_CHG_E 0x1c
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#define MAX77650_REG_CNFG_CHG_F 0x1d
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#define MAX77650_REG_CNFG_CHG_G 0x1e
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#define MAX77650_REG_CNFG_CHG_H 0x1f
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#define MAX77650_REG_CNFG_CHG_I 0x20
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#define MAX77650_REG_CNFG_SBB_TOP 0x28
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#define MAX77650_REG_CNFG_SBB0_A 0x29
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#define MAX77650_REG_CNFG_SBB0_B 0x2a
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#define MAX77650_REG_CNFG_SBB1_A 0x2b
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#define MAX77650_REG_CNFG_SBB1_B 0x2c
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#define MAX77650_REG_CNFG_SBB2_A 0x2d
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#define MAX77650_REG_CNFG_SBB2_B 0x2e
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#define MAX77650_REG_CNFG_LDO_A 0x38
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#define MAX77650_REG_CNFG_LDO_B 0x39
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#define MAX77650_REG_CNFG_LED0_A 0x40
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#define MAX77650_REG_CNFG_LED1_A 0x41
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#define MAX77650_REG_CNFG_LED2_A 0x42
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#define MAX77650_REG_CNFG_LED0_B 0x43
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#define MAX77650_REG_CNFG_LED1_B 0x44
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#define MAX77650_REG_CNFG_LED2_B 0x45
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#define MAX77650_REG_CNFG_LED_TOP 0x46
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#define MAX77650_CID_MASK GENMASK(3, 0)
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#define MAX77650_CID_BITS(_reg) (_reg & MAX77650_CID_MASK)
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#define MAX77650_CID_77650A 0x03
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#define MAX77650_CID_77650C 0x0a
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#define MAX77650_CID_77651A 0x06
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#define MAX77650_CID_77651B 0x08
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#endif /* MAX77650_H */
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