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alistair23-linux
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "MIPS updates:

   - All the things that didn't make 3.10.
   - Removes the Windriver PPMC platform.  Nobody will miss it.
   - Remove a workaround from kernel/irq/irqdomain.c which was there
     exclusivly for MIPS.  Patch by Grant Likely.
   - More small improvments for the SEAD 3 platform
   - Improvments on the BMIPS / SMP support for the BCM63xx series.
   - Various cleanups of dead leftovers.
   - Platform support for the Cavium Octeon-based EdgeRouter Lite.

  Two large KVM patchsets didn't make it for this pull request because
  their respective authors are vacationing"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (124 commits)
  MIPS: Kconfig: Add missing MODULES dependency to VPE_LOADER
  MIPS: BCM63xx: CLK: Add dummy clk_{set,round}_rate() functions
  MIPS: SEAD3: Disable L2 cache on SEAD-3.
  MIPS: BCM63xx: Enable second core SMP on BCM6328 if available
  MIPS: BCM63xx: Add SMP support to prom.c
  MIPS: define write{b,w,l,q}_relaxed
  MIPS: Expose missing pci_io{map,unmap} declarations
  MIPS: Malta: Update GCMP detection.
  Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"
  MIPS: APSP: Remove <asm/kspd.h>
  SSB: Kconfig: Amend SSB_EMBEDDED dependencies
  MIPS: microMIPS: Fix improper definition of ISA exception bit.
  MIPS: Don't try to decode microMIPS branch instructions where they cannot exist.
  MIPS: Declare emulate_load_store_microMIPS as a static function.
  MIPS: Fix typos and cleanup comment
  MIPS: Cleanup indentation and whitespace
  MIPS: BMIPS: support booting from physical CPU other than 0
  MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPS
  MIPS: GIC: Fix gic_set_affinity infinite loop
  MIPS: Don't save/restore OCTEON wide multiplier state on syscalls.
  ...
hifive-unleashed-5.1
Linus Torvalds 2013-07-13 14:52:21 -07:00
parent 833e68340d 6ac5310e64
commit d144746478
176 changed files with 2337 additions and 2412 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/mips/Kbuild.platforms
View File

@ -30,7 +30,6 @@ platforms += sibyte
platforms += sni
platforms += txx9
platforms += vr41xx
platforms += wrppmc
# include the platform specific files
include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))

76
arch/mips/Kconfig
View File

@ -1,6 +1,7 @@
config MIPS
bool
default y
select HAVE_CONTEXT_TRACKING
select HAVE_GENERIC_DMA_COHERENT
select HAVE_IDE
select HAVE_OPROFILE
@ -27,6 +28,7 @@ config MIPS
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
select GENERIC_PCI_IOMAP
select HAVE_ARCH_JUMP_LABEL
select ARCH_WANT_IPC_PARSE_VERSION
select IRQ_FORCED_THREADING
@ -46,9 +48,6 @@ config MIPS
menu "Machine selection"
config ZONE_DMA
bool
choice
prompt "System type"
default SGI_IP22
@ -124,11 +123,14 @@ config BCM47XX
config BCM63XX
bool "Broadcom BCM63XX based boards"
select BOOT_RAW
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
select NR_CPUS_DEFAULT_2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_HAS_EARLY_PRINTK
@ -341,7 +343,6 @@ config MIPS_SEAD3
select DMA_NONCOHERENT
select IRQ_CPU
select IRQ_GIC
select MIPS_CPU_SCACHE
select MIPS_MSC
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
@ -420,7 +421,6 @@ config POWERTV
select CSRC_POWERTV
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_HAS_EARLY_PRINTK
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
@ -713,46 +713,8 @@ config MIKROTIK_RB532
Support the Mikrotik(tm) RouterBoard 532 series,
based on the IDT RC32434 SoC.
config WR_PPMC
bool "Wind River PPMC board"
select CEVT_R4K
select CSRC_R4K
select IRQ_CPU
select BOOT_ELF32
select DMA_NONCOHERENT
select HW_HAS_PCI
select PCI_GT64XXX_PCI0
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS64_R1
select SYS_HAS_CPU_NEVADA
select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This enables support for the Wind River MIPS32 4KC PPMC evaluation
board, which is based on GT64120 bridge chip.
config CAVIUM_OCTEON_SIMULATOR
bool "Cavium Networks Octeon Simulator"
select CEVT_R4K
select 64BIT_PHYS_ADDR
select DMA_COHERENT
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HOTPLUG_CPU
select SYS_HAS_CPU_CAVIUM_OCTEON
select HOLES_IN_ZONE
help
The Octeon simulator is software performance model of the Cavium
Octeon Processor. It supports simulating Octeon processors on x86
hardware.
config CAVIUM_OCTEON_REFERENCE_BOARD
bool "Cavium Networks Octeon reference board"
config CAVIUM_OCTEON_SOC
bool "Cavium Networks Octeon SoC based boards"
select CEVT_R4K
select 64BIT_PHYS_ADDR
select DMA_COHERENT
@ -806,6 +768,8 @@ config NLM_XLR_BOARD
select SYS_HAS_EARLY_PRINTK
select USB_ARCH_HAS_OHCI if USB_SUPPORT
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select SYS_SUPPORTS_ZBOOT
select SYS_SUPPORTS_ZBOOT_UART16550
help
Support for systems based on Netlogic XLR and XLS processors.
Say Y here if you have a XLR or XLS based board.
@ -832,6 +796,8 @@ config NLM_XLP_BOARD
select SYNC_R4K
select SYS_HAS_EARLY_PRINTK
select USE_OF
select SYS_SUPPORTS_ZBOOT
select SYS_SUPPORTS_ZBOOT_UART16550
help
This board is based on Netlogic XLP Processor.
Say Y here if you have a XLP based board.
@ -1031,7 +997,6 @@ config CPU_BIG_ENDIAN
config CPU_LITTLE_ENDIAN
bool "Little endian"
depends on SYS_SUPPORTS_LITTLE_ENDIAN
help
endchoice
@ -1964,7 +1929,7 @@ config MIPS_MT_FPAFF
config MIPS_VPE_LOADER
bool "VPE loader support."
depends on SYS_SUPPORTS_MULTITHREADING
depends on SYS_SUPPORTS_MULTITHREADING && MODULES
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select MIPS_MT
@ -2382,6 +2347,19 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
config CC_STACKPROTECTOR
bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
help
This option turns on the -fstack-protector GCC feature. This
feature puts, at the beginning of functions, a canary value on
the stack just before the return address, and validates
the value just before actually returning. Stack based buffer
overflows (that need to overwrite this return address) now also
overwrite the canary, which gets detected and the attack is then
neutralized via a kernel panic.
This feature requires gcc version 4.2 or above.
config USE_OF
bool
select OF
@ -2413,7 +2391,6 @@ config PCI
bool "Support for PCI controller"
depends on HW_HAS_PCI
select PCI_DOMAINS
select GENERIC_PCI_IOMAP
select NO_GENERIC_PCI_IOPORT_MAP
help
Find out whether you have a PCI motherboard. PCI is the name of a
@ -2479,6 +2456,9 @@ config I8253
select CLKEVT_I8253
select MIPS_EXTERNAL_TIMER
config ZONE_DMA
bool
config ZONE_DMA32
bool

4
arch/mips/Makefile
View File

@ -227,6 +227,10 @@ KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
LDFLAGS += -m $(ld-emul)
ifdef CONFIG_CC_STACKPROTECTOR
KBUILD_CFLAGS += -fstack-protector
endif
ifdef CONFIG_MIPS
CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \
egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \

2
arch/mips/ath79/mach-ap136.c
View File

@ -132,7 +132,7 @@ static void __init ap136_pci_init(u8 *eeprom)
ath79_register_pci();
}
#else
static inline void ap136_pci_init(void) {}
static inline void ap136_pci_init(u8 *eeprom) {}
#endif /* CONFIG_PCI */
static void __init ap136_setup(void)

9
arch/mips/bcm63xx/Kconfig
View File

@ -1,6 +1,10 @@
menu "CPU support"
depends on BCM63XX
config BCM63XX_CPU_3368
bool "support 3368 CPU"
select HW_HAS_PCI
config BCM63XX_CPU_6328
bool "support 6328 CPU"
select HW_HAS_PCI
@ -8,14 +12,9 @@ config BCM63XX_CPU_6328
config BCM63XX_CPU_6338
bool "support 6338 CPU"
select HW_HAS_PCI
select USB_ARCH_HAS_OHCI
select USB_OHCI_BIG_ENDIAN_DESC
select USB_OHCI_BIG_ENDIAN_MMIO
config BCM63XX_CPU_6345
bool "support 6345 CPU"
select USB_OHCI_BIG_ENDIAN_DESC
select USB_OHCI_BIG_ENDIAN_MMIO
config BCM63XX_CPU_6348
bool "support 6348 CPU"

53
arch/mips/bcm63xx/boards/board_bcm963xx.c
View File

@ -28,10 +28,46 @@
#include <bcm63xx_dev_usb_usbd.h>
#include <board_bcm963xx.h>
#include <uapi/linux/bcm933xx_hcs.h>
#define PFX "board_bcm963xx: "
#define HCS_OFFSET_128K 0x20000
static struct board_info board;
/*
* known 3368 boards
*/
#ifdef CONFIG_BCM63XX_CPU_3368
static struct board_info __initdata board_cvg834g = {
.name = "CVG834G_E15R3921",
.expected_cpu_id = 0x3368,
.has_uart0 = 1,
.has_uart1 = 1,
.has_enet0 = 1,
.has_pci = 1,
.enet0 = {
.has_phy = 1,
.use_internal_phy = 1,
},
.leds = {
{
.name = "CVG834G:green:power",
.gpio = 37,
.default_trigger= "default-on",
},
},
.ephy_reset_gpio = 36,
.ephy_reset_gpio_flags = GPIOF_INIT_HIGH,
};
#endif
/*
* known 6328 boards
*/
@ -639,6 +675,9 @@ static struct board_info __initdata board_DWVS0 = {
* all boards
*/
static const struct board_info __initconst *bcm963xx_boards[] = {
#ifdef CONFIG_BCM63XX_CPU_3368
&board_cvg834g,
#endif
#ifdef CONFIG_BCM63XX_CPU_6328
&board_96328avng,
#endif
@ -722,8 +761,9 @@ void __init board_prom_init(void)
unsigned int i;
u8 *boot_addr, *cfe;
char cfe_version[32];
char *board_name;
char *board_name = NULL;
u32 val;
struct bcm_hcs *hcs;
/* read base address of boot chip select (0)
* 6328/6362 do not have MPI but boot from a fixed address
@ -747,7 +787,12 @@ void __init board_prom_init(void)
bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
board_name = bcm63xx_nvram_get_name();
if (BCMCPU_IS_3368()) {
hcs = (struct bcm_hcs *)boot_addr;
board_name = hcs->filename;
} else {
board_name = bcm63xx_nvram_get_name();
}
/* find board by name */
for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {
if (strncmp(board_name, bcm963xx_boards[i]->name, 16))
@ -877,5 +922,9 @@ int __init board_register_devices(void)
platform_device_register(&bcm63xx_gpio_leds);
if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags)
gpio_request_one(board.ephy_reset_gpio,
board.ephy_reset_gpio_flags, "ephy-reset");
return 0;
}

30
arch/mips/bcm63xx/clk.c
View File

@ -84,7 +84,7 @@ static void enetx_set(struct clk *clk, int enable)
else
clk_disable_unlocked(&clk_enet_misc);
if (BCMCPU_IS_6358()) {
if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
u32 mask;
if (clk->id == 0)
@ -110,9 +110,8 @@ static struct clk clk_enet1 = {
*/
static void ephy_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6358())
return;
bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
}
@ -155,9 +154,10 @@ static struct clk clk_enetsw = {
*/
static void pcm_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6358())
return;
bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
if (BCMCPU_IS_3368())
bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
if (BCMCPU_IS_6358())
bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
}
static struct clk clk_pcm = {
@ -211,7 +211,7 @@ static void spi_set(struct clk *clk, int enable)
mask = CKCTL_6338_SPI_EN;
else if (BCMCPU_IS_6348())
mask = CKCTL_6348_SPI_EN;
else if (BCMCPU_IS_6358())
else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
mask = CKCTL_6358_SPI_EN;
else if (BCMCPU_IS_6362())
mask = CKCTL_6362_SPI_EN;
@ -318,6 +318,18 @@ unsigned long clk_get_rate(struct clk *clk)
EXPORT_SYMBOL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
return 0;
}
EXPORT_SYMBOL_GPL(clk_set_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
return 0;
}
EXPORT_SYMBOL_GPL(clk_round_rate);
struct clk *clk_get(struct device *dev, const char *id)
{
if (!strcmp(id, "enet0"))
@ -338,7 +350,7 @@ struct clk *clk_get(struct device *dev, const char *id)
return &clk_xtm;
if (!strcmp(id, "periph"))
return &clk_periph;
if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
return &clk_pcm;
if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
return &clk_ipsec;

28
arch/mips/bcm63xx/cpu.c
View File

@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev;
static unsigned int bcm63xx_cpu_freq;
static unsigned int bcm63xx_memory_size;
static const unsigned long bcm3368_regs_base[] = {
__GEN_CPU_REGS_TABLE(3368)
};
static const int bcm3368_irqs[] = {
__GEN_CPU_IRQ_TABLE(3368)
};
static const unsigned long bcm6328_regs_base[] = {
__GEN_CPU_REGS_TABLE(6328)
};
@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(void)
static unsigned int detect_cpu_clock(void)
{
switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID:
return 300000000;
case BCM6328_CPU_ID:
{
unsigned int tmp, mips_pll_fcvo;
@ -266,7 +277,7 @@ static unsigned int detect_memory_size(void)
banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
}
if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
val = bcm_memc_readl(MEMC_CFG_REG);
rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@ -302,10 +313,17 @@ void __init bcm63xx_cpu_init(void)
chipid_reg = BCM_6345_PERF_BASE;
break;
case CPU_BMIPS4350:
if ((read_c0_prid() & 0xf0) == 0x10)
switch ((read_c0_prid() & 0xff)) {
case 0x04:
chipid_reg = BCM_3368_PERF_BASE;
break;
case 0x10:
chipid_reg = BCM_6345_PERF_BASE;
else
break;
default:
chipid_reg = BCM_6368_PERF_BASE;
break;
}
break;
}
@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void)
bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
switch (bcm63xx_cpu_id) {
case BCM3368_CPU_ID:
bcm63xx_regs_base = bcm3368_regs_base;
bcm63xx_irqs = bcm3368_irqs;
break;
case BCM6328_CPU_ID:
bcm63xx_regs_base = bcm6328_regs_base;
bcm63xx_irqs = bcm6328_irqs;

1
arch/mips/bcm63xx/dev-flash.c
View File

@ -71,6 +71,7 @@ static int __init bcm63xx_detect_flash_type(void)
case BCM6348_CPU_ID:
/* no way to auto detect so assume parallel */
return BCM63XX_FLASH_TYPE_PARALLEL;
case BCM3368_CPU_ID:
case BCM6358_CPU_ID:
val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)

6
arch/mips/bcm63xx/dev-spi.c
View File

@ -37,7 +37,8 @@ static __init void bcm63xx_spi_regs_init(void)
{
if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
bcm63xx_regs_spi = bcm6348_regs_spi;
if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
if (BCMCPU_IS_3368() || BCMCPU_IS_6358() ||
BCMCPU_IS_6362() || BCMCPU_IS_6368())
bcm63xx_regs_spi = bcm6358_regs_spi;
}
#else
@ -87,7 +88,8 @@ int __init bcm63xx_spi_register(void)
spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
}
if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
BCMCPU_IS_6368()) {
spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;

3
arch/mips/bcm63xx/dev-uart.c
View File

@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigned int id)
if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
return -ENODEV;
if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
if (id == 1 && (!BCMCPU_IS_3368() && !BCMCPU_IS_6358() &&
!BCMCPU_IS_6368()))
return -ENODEV;
if (id == 0) {

23
arch/mips/bcm63xx/irq.c
View File

@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
#ifndef BCMCPU_RUNTIME_DETECT
#ifdef CONFIG_BCM63XX_CPU_3368
#define irq_stat_reg PERF_IRQSTAT_3368_REG
#define irq_mask_reg PERF_IRQMASK_3368_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
#define ext_irq_end 0
#define ext_irq_count 4
#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6328
#define irq_stat_reg PERF_IRQSTAT_6328_REG
#define irq_mask_reg PERF_IRQMASK_6328_REG
@ -140,6 +151,13 @@ static void bcm63xx_init_irq(void)
irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_3368_REG;
irq_mask_addr += PERF_IRQMASK_3368_REG;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
break;
case BCM6328_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6328_REG;
irq_mask_addr += PERF_IRQMASK_6328_REG;
@ -294,6 +312,10 @@ asmlinkage void plat_irq_dispatch(void)
if (cause & CAUSEF_IP7)
do_IRQ(7);
if (cause & CAUSEF_IP0)
do_IRQ(0);
if (cause & CAUSEF_IP1)
do_IRQ(1);
if (cause & CAUSEF_IP2)
dispatch_internal();
if (!is_ext_irq_cascaded) {
@ -475,6 +497,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
break;
case BCM3368_CPU_ID:
case BCM6328_CPU_ID:
case BCM6338_CPU_ID:
case BCM6345_CPU_ID:

10
arch/mips/bcm63xx/nvram.c
View File

@ -42,6 +42,7 @@ void __init bcm63xx_nvram_init(void *addr)
{
unsigned int check_len;
u32 crc, expected_crc;
u8 hcs_mac_addr[ETH_ALEN] = { 0x00, 0x10, 0x18, 0xff, 0xff, 0xff };
/* extract nvram data */
memcpy(&nvram, addr, sizeof(nvram));
@ -62,6 +63,15 @@ void __init bcm63xx_nvram_init(void *addr)
if (crc != expected_crc)
pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
expected_crc, crc);
/* Cable modems have a different NVRAM which is embedded in the eCos
* firmware and not easily extractible, give at least a MAC address
* pool.
*/
if (BCMCPU_IS_3368()) {
memcpy(nvram.mac_addr_base, hcs_mac_addr, ETH_ALEN);
nvram.mac_addr_count = 2;
}
}
u8 *bcm63xx_nvram_get_name(void)

49
arch/mips/bcm63xx/prom.c
View File

@ -8,7 +8,11 @@
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/smp.h>
#include <asm/bootinfo.h>
#include <asm/bmips.h>
#include <asm/smp-ops.h>
#include <asm/mipsregs.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
@ -26,7 +30,9 @@ void __init prom_init(void)
bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
/* disable all hardware blocks clock for now */
if (BCMCPU_IS_6328())
if (BCMCPU_IS_3368())
mask = CKCTL_3368_ALL_SAFE_EN;
else if (BCMCPU_IS_6328())
mask = CKCTL_6328_ALL_SAFE_EN;
else if (BCMCPU_IS_6338())
mask = CKCTL_6338_ALL_SAFE_EN;
@ -52,6 +58,47 @@ void __init prom_init(void)
/* do low level board init */
board_prom_init();
if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
/* set up SMP */
register_smp_ops(&bmips_smp_ops);
/*
* BCM6328 might not have its second CPU enabled, while BCM6358
* needs special handling for its shared TLB, so disable SMP
* for now.
*/
if (BCMCPU_IS_6328()) {
reg = bcm_readl(BCM_6328_OTP_BASE +
OTP_USER_BITS_6328_REG(3));
if (reg & OTP_6328_REG3_TP1_DISABLED)
bmips_smp_enabled = 0;
} else if (BCMCPU_IS_6358()) {
bmips_smp_enabled = 0;
}
if (!bmips_smp_enabled)
return;
/*
* The bootloader has set up the CPU1 reset vector at
* 0xa000_0200.
* This conflicts with the special interrupt vector (IV).
* The bootloader has also set up CPU1 to respond to the wrong
* IPI interrupt.
* Here we will start up CPU1 in the background and ask it to
* reconfigure itself then go back to sleep.
*/
memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
__sync();
set_c0_cause(C_SW0);
cpumask_set_cpu(1, &bmips_booted_mask);
/*
* FIXME: we really should have some sort of hazard barrier here
*/
}
}
void __init prom_free_prom_memory(void)

29
arch/mips/bcm63xx/reset.c
View File

@ -30,6 +30,19 @@
[BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
[BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
#define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK
#define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK
#define BCM3368_RESET_USBH 0
#define BCM3368_RESET_USBD SOFTRESET_3368_USBS_MASK
#define BCM3368_RESET_DSL 0
#define BCM3368_RESET_SAR 0
#define BCM3368_RESET_EPHY SOFTRESET_3368_EPHY_MASK
#define BCM3368_RESET_ENETSW 0
#define BCM3368_RESET_PCM SOFTRESET_3368_PCM_MASK
#define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK
#define BCM3368_RESET_PCIE 0
#define BCM3368_RESET_PCIE_EXT 0
#define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
#define BCM6328_RESET_ENET 0
#define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
@ -117,6 +130,10 @@
/*
* core reset bits
*/
static const u32 bcm3368_reset_bits[] = {
__GEN_RESET_BITS_TABLE(3368)
};
static const u32 bcm6328_reset_bits[] = {
__GEN_RESET_BITS_TABLE(6328)
};
@ -146,7 +163,10 @@ static int reset_reg;
static int __init bcm63xx_reset_bits_init(void)
{
if (BCMCPU_IS_6328()) {
if (BCMCPU_IS_3368()) {
reset_reg = PERF_SOFTRESET_6358_REG;
bcm63xx_reset_bits = bcm3368_reset_bits;
} else if (BCMCPU_IS_6328()) {
reset_reg = PERF_SOFTRESET_6328_REG;
bcm63xx_reset_bits = bcm6328_reset_bits;
} else if (BCMCPU_IS_6338()) {
@ -170,6 +190,13 @@ static int __init bcm63xx_reset_bits_init(void)
}
#else
#ifdef CONFIG_BCM63XX_CPU_3368
static const u32 bcm63xx_reset_bits[] = {
__GEN_RESET_BITS_TABLE(3368)
};
#define reset_reg PERF_SOFTRESET_6358_REG
#endif
#ifdef CONFIG_BCM63XX_CPU_6328
static const u32 bcm63xx_reset_bits[] = {
__GEN_RESET_BITS_TABLE(6328)

3
arch/mips/bcm63xx/setup.c
View File

@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
/* mask and clear all external irq */
switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID:
perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
break;
case BCM6328_CPU_ID:
perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
break;

2
arch/mips/boot/compressed/Makefile
View File

@ -18,6 +18,8 @@ BOOT_HEAP_SIZE := 0x400000
# Disable Function Tracer
KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
KBUILD_CFLAGS := $(filter-out -fstack-protector, $(KBUILD_CFLAGS))
KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull"

22
arch/mips/boot/compressed/uart-16550.c
View File

@ -23,23 +23,39 @@
#define PORT(offset) (UART0_BASE + (4 * offset))
#endif
#ifdef CONFIG_CPU_XLR
#define UART0_BASE 0x1EF14000
#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
#define IOTYPE unsigned int
#endif
#ifdef CONFIG_CPU_XLP
#define UART0_BASE 0x18030100
#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
#define IOTYPE unsigned int
#endif
#ifndef IOTYPE
#define IOTYPE char
#endif
#ifndef PORT
#error please define the serial port address for your own machine
#endif
static inline unsigned int serial_in(int offset)
{
return *((char *)PORT(offset));
return *((volatile IOTYPE *)PORT(offset)) & 0xFF;
}
static inline void serial_out(int offset, int value)
{
*((char *)PORT(offset)) = value;
*((volatile IOTYPE *)PORT(offset)) = value & 0xFF;
}
void putc(char c)
{
int timeout = 1024;
int timeout = 1000000;
while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
;

17
arch/mips/cavium-octeon/Kconfig
View File

@ -10,6 +10,10 @@ config CAVIUM_CN63XXP1
non-CN63XXP1 hardware, so it is recommended to select "n"
unless it is known the workarounds are needed.
endif # CPU_CAVIUM_OCTEON
if CAVIUM_OCTEON_SOC
config CAVIUM_OCTEON_2ND_KERNEL
bool "Build the kernel to be used as a 2nd kernel on the same chip"
default "n"
@ -19,17 +23,6 @@ config CAVIUM_OCTEON_2ND_KERNEL
with this option to be run at the same time as one built without this
option.
config CAVIUM_OCTEON_HW_FIX_UNALIGNED
bool "Enable hardware fixups of unaligned loads and stores"
default "y"
help
Configure the Octeon hardware to automatically fix unaligned loads
and stores. Normally unaligned accesses are fixed using a kernel
exception handler. This option enables the hardware automatic fixups,
which requires only an extra 3 cycles. Disable this option if you
are running code that relies on address exceptions on unaligned
accesses.
config CAVIUM_OCTEON_CVMSEG_SIZE
int "Number of L1 cache lines reserved for CVMSEG memory"
range 0 54
@ -103,4 +96,4 @@ config OCTEON_ILM
To compile this driver as a module, choose M here. The module
will be called octeon-ilm
endif # CPU_CAVIUM_OCTEON
endif # CAVIUM_OCTEON_SOC

5
arch/mips/cavium-octeon/Makefile
View File

@ -12,11 +12,12 @@
CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt
CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y += dma-octeon.o flash_setup.o
obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y += dma-octeon.o
obj-y += octeon-memcpy.o
obj-y += executive/
obj-$(CONFIG_MTD) += flash_setup.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o

8
arch/mips/cavium-octeon/Platform
View File

@ -1,11 +1,11 @@
#
# Cavium Octeon
#
platform-$(CONFIG_CPU_CAVIUM_OCTEON) += cavium-octeon/
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += \
platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/
cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \
-I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000
load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff84100000
else
load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000
endif

13
arch/mips/cavium-octeon/executive/cvmx-helper-board.c
View File

@ -181,6 +181,11 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
return ipd_port - 16 + 4;
else
return -1;
case CVMX_BOARD_TYPE_UBNT_E100:
if (ipd_port >= 0 && ipd_port <= 2)
return 7 - ipd_port;
else
return -1;
}
/* Some unknown board. Somebody forgot to update this function... */
@ -706,6 +711,14 @@ int __cvmx_helper_board_hardware_enable(int interface)
}
}
}
} else if (cvmx_sysinfo_get()->board_type ==
CVMX_BOARD_TYPE_UBNT_E100) {
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0);
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10);
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10);
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0);
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10);
}
return 0;
}

9
arch/mips/cavium-octeon/octeon-platform.c
View File

@ -490,8 +490,15 @@ int __init octeon_prune_device_tree(void)
if (alias_prop) {
uart = fdt_path_offset(initial_boot_params, alias_prop);
if (uart_mask & (1 << i))
if (uart_mask & (1 << i)) {
__be32 f;
f = cpu_to_be32(octeon_get_io_clock_rate());
fdt_setprop_inplace(initial_boot_params,
uart, "clock-frequency",
&f, sizeof(f));
continue;
}
pr_debug("Deleting uart%d\n", i);
fdt_nop_node(initial_boot_params, uart);
fdt_nop_property(initial_boot_params, aliases,

109
arch/mips/cavium-octeon/serial.c
View File

@ -1,109 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004-2007 Cavium Networks
*/
#include <linux/console.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/tty.h>
#include <linux/irq.h>
#include <asm/time.h>
#include <asm/octeon/octeon.h>
#define DEBUG_UART 1
unsigned int octeon_serial_in(struct uart_port *up, int offset)
{
int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
if (offset == UART_IIR && (rv & 0xf) == 7) {
/* Busy interrupt, read the USR (39) and try again. */
cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
}
return rv;
}
void octeon_serial_out(struct uart_port *up, int offset, int value)
{
/*
* If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
* working.
*/
if (offset == UART_LCR)
value &= 0x9f;
cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
}
static int octeon_serial_probe(struct platform_device *pdev)
{
int irq, res;
struct resource *res_mem;
struct uart_8250_port up;
/* All adaptors have an irq. */
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
memset(&up, 0, sizeof(up));
up.port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
up.port.type = PORT_OCTEON;
up.port.iotype = UPIO_MEM;
up.port.regshift = 3;
up.port.dev = &pdev->dev;
if (octeon_is_simulation())
/* Make simulator output fast*/
up.port.uartclk = 115200 * 16;
else
up.port.uartclk = octeon_get_io_clock_rate();
up.port.serial_in = octeon_serial_in;
up.port.serial_out = octeon_serial_out;
up.port.irq = irq;
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res_mem == NULL) {
dev_err(&pdev->dev, "found no memory resource\n");
return -ENXIO;
}
up.port.mapbase = res_mem->start;
up.port.membase = ioremap(res_mem->start, resource_size(res_mem));
res = serial8250_register_8250_port(&up);
return res >= 0 ? 0 : res;
}
static struct of_device_id octeon_serial_match[] = {
{
.compatible = "cavium,octeon-3860-uart",
},
{},
};
MODULE_DEVICE_TABLE(of, octeon_serial_match);
static struct platform_driver octeon_serial_driver = {
.probe = octeon_serial_probe,
.driver = {
.owner = THIS_MODULE,
.name = "octeon_serial",
.of_match_table = octeon_serial_match,
},
};
static int __init octeon_serial_init(void)
{
return platform_driver_register(&octeon_serial_driver);
}
late_initcall(octeon_serial_init);

32
arch/mips/cavium-octeon/setup.c
View File

@ -7,6 +7,7 @@
* Copyright (C) 2008, 2009 Wind River Systems
* written by Ralf Baechle <ralf@linux-mips.org>
*/
#include <linux/compiler.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/console.h>
@ -40,12 +41,6 @@
#include <asm/octeon/pci-octeon.h>
#include <asm/octeon/cvmx-mio-defs.h>
#ifdef CONFIG_CAVIUM_DECODE_RSL
extern void cvmx_interrupt_rsl_decode(void);
extern int __cvmx_interrupt_ecc_report_single_bit_errors;
extern void cvmx_interrupt_rsl_enable(void);
#endif
extern struct plat_smp_ops octeon_smp_ops;
#ifdef CONFIG_PCI
@ -462,18 +457,6 @@ static void octeon_halt(void)
octeon_kill_core(NULL);
}
/**
* Handle all the error condition interrupts that might occur.
*
*/
#ifdef CONFIG_CAVIUM_DECODE_RSL
static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
{
cvmx_interrupt_rsl_decode();
return IRQ_HANDLED;
}
#endif
/**
* Return a string representing the system type
*
@ -712,7 +695,7 @@ void __init prom_init(void)
if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
pr_info("Skipping L2 locking due to reduced L2 cache size\n");
} else {
uint32_t ebase = read_c0_ebase() & 0x3ffff000;
uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
/* TLB refill */
cvmx_l2c_lock_mem_region(ebase, 0x100);
@ -996,7 +979,7 @@ void __init plat_mem_setup(void)
cvmx_bootmem_unlock();
/* Add the memory region for the kernel. */
kernel_start = (unsigned long) _text;
kernel_size = ALIGN(_end - _text, 0x100000);
kernel_size = _end - _text;
/* Adjust for physical offset. */
kernel_start &= ~0xffffffff80000000ULL;
@ -1064,15 +1047,6 @@ void prom_free_prom_memory(void)
panic("Core-14449 WAR not in place (%04x).\n"
"Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
}
#ifdef CONFIG_CAVIUM_DECODE_RSL
cvmx_interrupt_rsl_enable();
/* Add an interrupt handler for general failures. */
if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
"RML/RSL", octeon_rlm_interrupt)) {
panic("Unable to request_irq(OCTEON_IRQ_RML)");
}
#endif
}
int octeon_prune_device_tree(void);

6
arch/mips/configs/cavium_octeon_defconfig
View File

@ -1,13 +1,11 @@
CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y
CONFIG_CAVIUM_OCTEON_SOC=y
CONFIG_CAVIUM_CN63XXP1=y
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_SMP=y
CONFIG_NR_CPUS=32
CONFIG_HZ_100=y
CONFIG_PREEMPT=y
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
@ -50,7 +48,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
# CONFIG_MTD_OF_PARTS is not set
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
@ -114,6 +111,7 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_DW=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_OCTEON=y

97
arch/mips/configs/wrppmc_defconfig
View File

@ -1,97 +0,0 @@
CONFIG_WR_PPMC=y
CONFIG_HZ_1000=y
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
CONFIG_KALLSYMS_EXTRA_PASS=y
# CONFIG_EPOLL is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_PCI=y
CONFIG_HOTPLUG_PCI=y
CONFIG_BINFMT_MISC=y
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_IP_MROUTE=y
CONFIG_ARPD=y
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_XFRM_MODE_BEET=m
CONFIG_TCP_MD5SIG=y
# CONFIG_IPV6 is not set
CONFIG_NETWORK_SECMARK=y
CONFIG_FW_LOADER=m
CONFIG_BLK_DEV_RAM=y
CONFIG_SGI_IOC4=m
CONFIG_NETDEVICES=y
CONFIG_PHYLIB=y
CONFIG_VITESSE_PHY=m
CONFIG_SMSC_PHY=m
CONFIG_NET_ETHERNET=y
CONFIG_NET_PCI=y
CONFIG_E100=y
CONFIG_QLA3XXX=m
CONFIG_CHELSIO_T3=m
CONFIG_NETXEN_NIC=m
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
# CONFIG_HW_RANDOM is not set
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_DLM=m
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyS0,115200n8"
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_LIBCRC32C=y

1
arch/mips/dec/Makefile
View File

@ -5,6 +5,5 @@
obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
kn02-irq.o kn02xa-berr.o reset.o setup.o time.o
obj-$(CONFIG_PROM_CONSOLE) += promcon.o
obj-$(CONFIG_TC) += tc.o
obj-$(CONFIG_CPU_HAS_WB) += wbflush.o

54
arch/mips/dec/promcon.c
View File

@ -1,54 +0,0 @@
/*
* Wrap-around code for a console using the
* DECstation PROM io-routines.
*
* Copyright (c) 1998 Harald Koerfgen
*/
#include <linux/tty.h>
#include <linux/ptrace.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/fs.h>
#include <asm/dec/prom.h>
static void prom_console_write(struct console *co, const char *s,
unsigned count)
{
unsigned i;
/*
* Now, do each character
*/
for (i = 0; i < count; i++) {
if (*s == 10)
prom_printf("%c", 13);
prom_printf("%c", *s++);
}
}
static int __init prom_console_setup(struct console *co, char *options)
{
return 0;
}
static struct console sercons = {
.name = "ttyS",
.write = prom_console_write,
.setup = prom_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
};
/*
* Register console.
*/
static int __init prom_console_init(void)
{
register_console(&sercons);
return 0;
}
console_initcall(prom_console_init);

4
arch/mips/fw/cfe/cfe_api.c
View File

@ -406,12 +406,12 @@ int cfe_setenv(char *name, char *val)
return xiocb.xiocb_status;
}
int cfe_write(int handle, unsigned char *buffer, int length)
int cfe_write(int handle, const char *buffer, int length)
{
return cfe_writeblk(handle, 0, buffer, length);
}
int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length)
int cfe_writeblk(int handle, s64 offset, const char *buffer, int length)
{
struct cfe_xiocb xiocb;

29
arch/mips/include/asm/cop2.h
View File

@ -11,6 +11,35 @@
#include <linux/notifier.h>
#if defined(CONFIG_CPU_CAVIUM_OCTEON)
extern void octeon_cop2_save(struct octeon_cop2_state *);
extern void octeon_cop2_restore(struct octeon_cop2_state *);
#define cop2_save(r) octeon_cop2_save(r)
#define cop2_restore(r) octeon_cop2_restore(r)
#define cop2_present 1
#define cop2_lazy_restore 1
#elif defined(CONFIG_CPU_XLP)
extern void nlm_cop2_save(struct nlm_cop2_state *);
extern void nlm_cop2_restore(struct nlm_cop2_state *);
#define cop2_save(r) nlm_cop2_save(r)
#define cop2_restore(r) nlm_cop2_restore(r)
#define cop2_present 1
#define cop2_lazy_restore 0
#else
#define cop2_present 0
#define cop2_lazy_restore 0
#define cop2_save(r)
#define cop2_restore(r)
#endif
enum cu2_ops {
CU2_EXCEPTION,
CU2_LWC2_OP,

49
arch/mips/include/asm/cpu-features.h
View File

@ -24,6 +24,16 @@
#ifndef cpu_has_tlb
#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
#endif
/*
* For the moment we don't consider R6000 and R8000 so we can assume that
* anything that doesn't support R4000-style exceptions and interrupts is
* R3000-like. Users should still treat these two macro definitions as
* opaque.
*/
#ifndef cpu_has_3kex
#define cpu_has_3kex (!cpu_has_4kex)
#endif
#ifndef cpu_has_4kex
#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
#endif
@ -87,19 +97,23 @@
#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
#endif
#ifndef cpu_has_mdmx
#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
#endif
#ifndef cpu_has_mips3d
#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
#endif
#ifndef cpu_has_smartmips
#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#endif
#ifndef cpu_has_rixi
#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
#endif
#ifndef cpu_has_mmips
#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
# else
# define cpu_has_mmips 0
# endif
#endif
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
@ -111,7 +125,7 @@
#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
#endif
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
#ifndef cpu_has_local_ebase
#define cpu_has_local_ebase 1
@ -136,7 +150,6 @@
#endif
#endif
# define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I)
#ifndef cpu_has_mips_2
# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
#endif
@ -149,18 +162,18 @@
#ifndef cpu_has_mips_5
# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
#endif
# ifndef cpu_has_mips32r1
#ifndef cpu_has_mips32r1
# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
# endif
# ifndef cpu_has_mips32r2
#endif
#ifndef cpu_has_mips32r2
# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
# endif
# ifndef cpu_has_mips64r1
#endif
#ifndef cpu_has_mips64r1
# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
# endif
# ifndef cpu_has_mips64r2
#endif
#ifndef cpu_has_mips64r2
# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
# endif
#endif
/*
* Shortcuts ...
@ -182,9 +195,9 @@
* has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
*/
# ifndef cpu_has_clo_clz
# define cpu_has_clo_clz cpu_has_mips_r
# endif
#ifndef cpu_has_clo_clz
#define cpu_has_clo_clz cpu_has_mips_r
#endif
#ifndef cpu_has_dsp
#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
@ -210,7 +223,7 @@
# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs 0

21
arch/mips/include/asm/cpu.h
View File

@ -282,18 +282,17 @@ enum cpu_type_enum {
* ISA Level encodings
*
*/
#define MIPS_CPU_ISA_I 0x00000001
#define MIPS_CPU_ISA_II 0x00000002
#define MIPS_CPU_ISA_III 0x00000004
#define MIPS_CPU_ISA_IV 0x00000008
#define MIPS_CPU_ISA_V 0x00000010
#define MIPS_CPU_ISA_M32R1 0x00000020
#define MIPS_CPU_ISA_M32R2 0x00000040
#define MIPS_CPU_ISA_M64R1 0x00000080
#define MIPS_CPU_ISA_M64R2 0x00000100
#define MIPS_CPU_ISA_II 0x00000001
#define MIPS_CPU_ISA_III 0x00000002
#define MIPS_CPU_ISA_IV 0x00000004
#define MIPS_CPU_ISA_V 0x00000008
#define MIPS_CPU_ISA_M32R1 0x00000010
#define MIPS_CPU_ISA_M32R2 0x00000020
#define MIPS_CPU_ISA_M64R1 0x00000040
#define MIPS_CPU_ISA_M64R2 0x00000080
#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2)
#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
MIPS_CPU_ISA_M32R2)
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)

4
arch/mips/include/asm/fw/cfe/cfe_api.h
View File

@ -115,8 +115,8 @@ int cfe_read(int handle, unsigned char *buffer, int length);
int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
int length);
int cfe_setenv(char *name, char *val);
int cfe_write(int handle, unsigned char *buffer, int length);
int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer,
int cfe_write(int handle, const char *buffer, int length);
int cfe_writeblk(int handle, int64_t offset, const char *buffer,
int length);
#endif /* CFE_API_H */

2
arch/mips/include/asm/gic.h
View File

@ -347,7 +347,7 @@ struct gic_shared_intr_map {
#define GIC_CPU_INT2 2 /* . */
#define GIC_CPU_INT3 3 /* . */
#define GIC_CPU_INT4 4 /* . */
#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
/* Local GIC interrupts. */
#define GIC_INT_TMR (GIC_CPU_INT5)

10
arch/mips/include/asm/io.h
View File

@ -170,6 +170,11 @@ static inline void * isa_bus_to_virt(unsigned long address)
extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
extern void __iounmap(const volatile void __iomem *addr);
#ifndef CONFIG_PCI
struct pci_dev;
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
#endif
static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
unsigned long flags)
{
@ -449,6 +454,11 @@ __BUILDIO(q, u64)
#define readl_relaxed readl
#define readq_relaxed readq
#define writeb_relaxed writeb
#define writew_relaxed writew
#define writel_relaxed writel
#define writeq_relaxed writeq
#define readb_be(addr) \
__raw_readb((__force unsigned *)(addr))
#define readw_be(addr) \

32
arch/mips/include/asm/kspd.h
View File

@ -1,32 +0,0 @@
/*
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
*/
#ifndef _ASM_KSPD_H
#define _ASM_KSPD_H
struct kspd_notifications {
void (*kspd_sp_exit)(int sp_id);
struct list_head list;
};
static inline void kspd_notify(struct kspd_notifications *notify)
{
}
#endif

7
arch/mips/include/asm/mach-ar7/spaces.h
View File

@ -14,8 +14,11 @@
* This handles the memory map.
* We handle pages at KSEG0 for kernels with 32 bit address space.
*/
#define PAGE_OFFSET 0x94000000UL
#define PHYS_OFFSET 0x14000000UL
#define PAGE_OFFSET _AC(0x94000000, UL)
#define PHYS_OFFSET _AC(0x14000000, UL)
#define UNCAC_BASE _AC(0xb4000000, UL) /* 0xa0000000 + PHYS_OFFSET */
#define IO_BASE UNCAC_BASE
#include <asm/mach-generic/spaces.h>

112
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
View File

@ -9,6 +9,7 @@
* compile time if only one CPU support is enabled (idea stolen from
* arm mach-types)
*/
#define BCM3368_CPU_ID 0x3368
#define BCM6328_CPU_ID 0x6328
#define BCM6338_CPU_ID 0x6338
#define BCM6345_CPU_ID 0x6345
@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
u8 bcm63xx_get_cpu_rev(void);
unsigned int bcm63xx_get_cpu_freq(void);
#ifdef CONFIG_BCM63XX_CPU_3368
# ifdef bcm63xx_get_cpu_id
# undef bcm63xx_get_cpu_id
# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
# define BCMCPU_RUNTIME_DETECT
# else
# define bcm63xx_get_cpu_id() BCM3368_CPU_ID
# endif
# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
#else
# define BCMCPU_IS_3368() (0)
#endif
#ifdef CONFIG_BCM63XX_CPU_6328
# ifdef bcm63xx_get_cpu_id
# undef bcm63xx_get_cpu_id
@ -193,6 +207,53 @@ enum bcm63xx_regs_set {
#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
#define RSET_RNG_SIZE 20
/*
* 3368 register sets base address
*/
#define BCM_3368_DSL_LMEM_BASE (0xdeadbeef)
#define BCM_3368_PERF_BASE (0xfff8c000)
#define BCM_3368_TIMER_BASE (0xfff8c040)
#define BCM_3368_WDT_BASE (0xfff8c080)
#define BCM_3368_UART0_BASE (0xfff8c100)
#define BCM_3368_UART1_BASE (0xfff8c120)
#define BCM_3368_GPIO_BASE (0xfff8c080)
#define BCM_3368_SPI_BASE (0xfff8c800)
#define BCM_3368_HSSPI_BASE (0xdeadbeef)
#define BCM_3368_UDC0_BASE (0xdeadbeef)
#define BCM_3368_USBDMA_BASE (0xdeadbeef)
#define BCM_3368_OHCI0_BASE (0xdeadbeef)
#define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef)
#define BCM_3368_USBH_PRIV_BASE (0xdeadbeef)
#define BCM_3368_USBD_BASE (0xdeadbeef)
#define BCM_3368_MPI_BASE (0xfff80000)
#define BCM_3368_PCMCIA_BASE (0xfff80054)
#define BCM_3368_PCIE_BASE (0xdeadbeef)
#define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef)
#define BCM_3368_DSL_BASE (0xdeadbeef)
#define BCM_3368_UBUS_BASE (0xdeadbeef)
#define BCM_3368_ENET0_BASE (0xfff98000)
#define BCM_3368_ENET1_BASE (0xfff98800)
#define BCM_3368_ENETDMA_BASE (0xfff99800)
#define BCM_3368_ENETDMAC_BASE (0xfff99900)
#define BCM_3368_ENETDMAS_BASE (0xfff99a00)
#define BCM_3368_ENETSW_BASE (0xdeadbeef)
#define BCM_3368_EHCI0_BASE (0xdeadbeef)
#define BCM_3368_SDRAM_BASE (0xdeadbeef)
#define BCM_3368_MEMC_BASE (0xfff84000)
#define BCM_3368_DDR_BASE (0xdeadbeef)
#define BCM_3368_M2M_BASE (0xdeadbeef)
#define BCM_3368_ATM_BASE (0xdeadbeef)
#define BCM_3368_XTM_BASE (0xdeadbeef)
#define BCM_3368_XTMDMA_BASE (0xdeadbeef)
#define BCM_3368_XTMDMAC_BASE (0xdeadbeef)
#define BCM_3368_XTMDMAS_BASE (0xdeadbeef)
#define BCM_3368_PCM_BASE (0xfff9c200)
#define BCM_3368_PCMDMA_BASE (0xdeadbeef)
#define BCM_3368_PCMDMAC_BASE (0xdeadbeef)
#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
#define BCM_3368_RNG_BASE (0xdeadbeef)
#define BCM_3368_MISC_BASE (0xdeadbeef)
/*
* 6328 register sets base address
*/
@ -238,6 +299,8 @@ enum bcm63xx_regs_set {
#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
#define BCM_6328_RNG_BASE (0xdeadbeef)
#define BCM_6328_MISC_BASE (0xb0001800)
#define BCM_6328_OTP_BASE (0xb0000600)
/*
* 6338 register sets base address
*/
@ -623,6 +686,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
#ifdef BCMCPU_RUNTIME_DETECT
return bcm63xx_regs_base[set];
#else
#ifdef CONFIG_BCM63XX_CPU_3368
__GEN_RSET(3368)
#endif
#ifdef CONFIG_BCM63XX_CPU_6328
__GEN_RSET(6328)
#endif
@ -689,6 +755,52 @@ enum bcm63xx_irq {
IRQ_XTM_DMA0,
};
/*
* 3368 irqs
*/
#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_3368_DSL_IRQ 0
#define BCM_3368_UDC0_IRQ 0
#define BCM_3368_OHCI0_IRQ 0
#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
#define BCM_3368_HSSPI_IRQ 0
#define BCM_3368_EHCI0_IRQ 0
#define BCM_3368_USBD_IRQ 0
#define BCM_3368_USBD_RXDMA0_IRQ 0
#define BCM_3368_USBD_TXDMA0_IRQ 0
#define BCM_3368_USBD_RXDMA1_IRQ 0
#define BCM_3368_USBD_TXDMA1_IRQ 0
#define BCM_3368_USBD_RXDMA2_IRQ 0
#define BCM_3368_USBD_TXDMA2_IRQ 0
#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
#define BCM_3368_PCMCIA_IRQ 0
#define BCM_3368_ATM_IRQ 0
#define BCM_3368_ENETSW_RXDMA0_IRQ 0
#define BCM_3368_ENETSW_RXDMA1_IRQ 0
#define BCM_3368_ENETSW_RXDMA2_IRQ 0
#define BCM_3368_ENETSW_RXDMA3_IRQ 0
#define BCM_3368_ENETSW_TXDMA0_IRQ 0
#define BCM_3368_ENETSW_TXDMA1_IRQ 0
#define BCM_3368_ENETSW_TXDMA2_IRQ 0
#define BCM_3368_ENETSW_TXDMA3_IRQ 0
#define BCM_3368_XTM_IRQ 0
#define BCM_3368_XTM_DMA0_IRQ 0
#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
/*
* 6328 irqs
*/

1
arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
View File

@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio_count(void)
switch (bcm63xx_get_cpu_id()) {
case BCM6328_CPU_ID:
return 32;
case BCM3368_CPU_ID:
case BCM6358_CPU_ID:
return 40;
case BCM6338_CPU_ID:

52
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
View File

@ -15,6 +15,39 @@
/* Clock Control register */
#define PERF_CKCTL_REG 0x4
#define CKCTL_3368_MAC_EN (1 << 3)
#define CKCTL_3368_TC_EN (1 << 5)
#define CKCTL_3368_US_TOP_EN (1 << 6)
#define CKCTL_3368_DS_TOP_EN (1 << 7)
#define CKCTL_3368_APM_EN (1 << 8)
#define CKCTL_3368_SPI_EN (1 << 9)
#define CKCTL_3368_USBS_EN (1 << 10)
#define CKCTL_3368_BMU_EN (1 << 11)
#define CKCTL_3368_PCM_EN (1 << 12)
#define CKCTL_3368_NTP_EN (1 << 13)
#define CKCTL_3368_ACP_B_EN (1 << 14)
#define CKCTL_3368_ACP_A_EN (1 << 15)
#define CKCTL_3368_EMUSB_EN (1 << 17)
#define CKCTL_3368_ENET0_EN (1 << 18)
#define CKCTL_3368_ENET1_EN (1 << 19)
#define CKCTL_3368_USBU_EN (1 << 20)
#define CKCTL_3368_EPHY_EN (1 << 21)
#define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \
CKCTL_3368_TC_EN | \
CKCTL_3368_US_TOP_EN | \
CKCTL_3368_DS_TOP_EN | \
CKCTL_3368_APM_EN | \
CKCTL_3368_SPI_EN | \
CKCTL_3368_USBS_EN | \
CKCTL_3368_BMU_EN | \
CKCTL_3368_PCM_EN | \
CKCTL_3368_NTP_EN | \
CKCTL_3368_ACP_B_EN | \
CKCTL_3368_ACP_A_EN | \
CKCTL_3368_EMUSB_EN | \
CKCTL_3368_USBU_EN)
#define CKCTL_6328_PHYMIPS_EN (1 << 0)
#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
@ -181,6 +214,7 @@
#define SYS_PLL_SOFT_RESET 0x1
/* Interrupt Mask register */
#define PERF_IRQMASK_3368_REG 0xc
#define PERF_IRQMASK_6328_REG 0x20
#define PERF_IRQMASK_6338_REG 0xc
#define PERF_IRQMASK_6345_REG 0xc
@ -190,6 +224,7 @@
#define PERF_IRQMASK_6368_REG 0x20
/* Interrupt Status register */
#define PERF_IRQSTAT_3368_REG 0x10
#define PERF_IRQSTAT_6328_REG 0x28
#define PERF_IRQSTAT_6338_REG 0x10
#define PERF_IRQSTAT_6345_REG 0x10
@ -199,6 +234,7 @@
#define PERF_IRQSTAT_6368_REG 0x28
/* External Interrupt Configuration register */
#define PERF_EXTIRQ_CFG_REG_3368 0x14
#define PERF_EXTIRQ_CFG_REG_6328 0x18
#define PERF_EXTIRQ_CFG_REG_6338 0x14
#define PERF_EXTIRQ_CFG_REG_6345 0x14
@ -236,6 +272,13 @@
#define PERF_SOFTRESET_6362_REG 0x10
#define PERF_SOFTRESET_6368_REG 0x10
#define SOFTRESET_3368_SPI_MASK (1 << 0)
#define SOFTRESET_3368_ENET_MASK (1 << 2)
#define SOFTRESET_3368_MPI_MASK (1 << 3)
#define SOFTRESET_3368_EPHY_MASK (1 << 6)
#define SOFTRESET_3368_USBS_MASK (1 << 11)
#define SOFTRESET_3368_PCM_MASK (1 << 13)
#define SOFTRESET_6328_SPI_MASK (1 << 0)
#define SOFTRESET_6328_EPHY_MASK (1 << 1)
#define SOFTRESET_6328_SAR_MASK (1 << 2)
@ -1370,7 +1413,7 @@
#define SPI_6348_RX_DATA 0x80
#define SPI_6348_RX_DATA_SIZE 0x3f
/* BCM 6358/6262/6368 SPI core */
/* BCM 3368/6358/6262/6368 SPI core */
#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
#define SPI_6358_MSG_CTL_WIDTH 16
#define SPI_6358_MSG_DATA 0x02
@ -1511,4 +1554,11 @@
#define PCIE_DEVICE_OFFSET 0x8000
/*************************************************************************
* _REG relative to RSET_OTP
*************************************************************************/
#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
#define OTP_6328_REG3_TP1_DISABLED BIT(9)
#endif /* BCM63XX_REGS_H_ */

6
arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
View File

@ -47,6 +47,12 @@ struct board_info {
/* GPIO LEDs */
struct gpio_led leds[5];
/* External PHY reset GPIO */
unsigned int ephy_reset_gpio;
/* External PHY reset GPIO flags from gpio.h */
unsigned long ephy_reset_gpio_flags;
};
#endif /* ! BOARD_BCM963XX_H_ */

4
arch/mips/include/asm/mach-bcm63xx/ioremap.h
View File

@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
static inline int is_bcm63xx_internal_registers(phys_t offset)
{
switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID:
if (offset >= 0xfff80000)
return 1;
break;
case BCM6338_CPU_ID:
case BCM6345_CPU_ID:
case BCM6348_CPU_ID:

7
arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
View File

@ -13,6 +13,8 @@
#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
#include <linux/bug.h>
struct device;
extern void octeon_pci_dma_init(void);
@ -21,18 +23,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
BUG();
return 0;
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
BUG();
return 0;
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
BUG();
return 0;
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
@ -44,6 +49,7 @@ static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
BUG();
return 0;
}
static inline void plat_extra_sync_for_device(struct device *dev)
@ -60,6 +66,7 @@ static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
BUG();
return 0;
}
dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);

7
arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
View File

@ -34,15 +34,10 @@
ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
# Disable unaligned load/store support but leave HW fixup enabled
# Needed for octeon specific memcpy
or v0, v0, 0x5001
xor v0, v0, 0x1001
#else
# Disable unaligned load/store and HW fixup support
or v0, v0, 0x5001
xor v0, v0, 0x5001
#endif
# Read the processor ID register
mfc0 v1, CP0_PRID_REG
# Disable instruction prefetching (Octeon Pass1 errata)

24
arch/mips/include/asm/mach-cavium-octeon/spaces.h 100644
View File

@ -0,0 +1,24 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2012 Cavium, Inc.
*/
#ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H
#define _ASM_MACH_CAVIUM_OCTEON_SPACES_H
#include <linux/const.h>
#ifdef CONFIG_64BIT
/* They are all the same and some OCTEON II cores cannot handle 0xa8.. */
#define CAC_BASE _AC(0x8000000000000000, UL)
#define UNCAC_BASE _AC(0x8000000000000000, UL)
#define IO_BASE _AC(0x8000000000000000, UL)
#endif /* CONFIG_64BIT */
#include <asm/mach-generic/spaces.h>
#endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */

12
arch/mips/include/asm/mach-generic/dma-coherence.h
View File

@ -66,4 +66,16 @@ static inline int plat_device_is_coherent(struct device *dev)
#endif
}
#ifdef CONFIG_SWIOTLB
static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
{
return paddr;
}
static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
{
return daddr;
}
#endif
#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */

4
arch/mips/include/asm/mach-generic/kernel-entry-init.h
View File

@ -12,8 +12,8 @@
/* Intentionally empty macro, used in head.S. Override in
* arch/mips/mach-xxx/kernel-entry-init.h when necessary.
*/
.macro kernel_entry_setup
.endm
.macro kernel_entry_setup
.endm
/*
* Do SMP slave processor setup necessary before we can savely execute C code.

47
arch/mips/include/asm/mach-ip27/kernel-entry-init.h
View File

@ -23,6 +23,53 @@
dsrl \res, NSRI_NODEID_SHFT
.endm
/*
* TLB bits
*/
#define PAGE_GLOBAL (1 << 6)
#define PAGE_VALID (1 << 7)
#define PAGE_DIRTY (1 << 8)
#define CACHE_CACHABLE_COW (5 << 9)
/*
* inputs are the text nasid in t1, data nasid in t2.
*/
.macro MAPPED_KERNEL_SETUP_TLB
#ifdef CONFIG_MAPPED_KERNEL
/*
* This needs to read the nasid - assume 0 for now.
* Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
* 0+DVG in tlblo_1.
*/
dli t0, 0xffffffffc0000000
dmtc0 t0, CP0_ENTRYHI
li t0, 0x1c000 # Offset of text into node memory
dsll t1, NASID_SHFT # Shift text nasid into place
dsll t2, NASID_SHFT # Same for data nasid
or t1, t1, t0 # Physical load address of kernel text
or t2, t2, t0 # Physical load address of kernel data
dsrl t1, 12 # 4K pfn
dsrl t2, 12 # 4K pfn
dsll t1, 6 # Get pfn into place
dsll t2, 6 # Get pfn into place
li t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6)
or t0, t0, t1
mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
li t0, ((PAGE_GLOBAL | PAGE_VALID | PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6)
or t0, t0, t2
mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
mtc0 t0, CP0_PAGEMASK
li t0, 0 # KMAP_INX
mtc0 t0, CP0_INDEX
li t0, 1
mtc0 t0, CP0_WIRED
tlbwi
#else
mtc0 zero, CP0_WIRED
#endif
.endm
/*
* Intentionally empty macro, used in head.S. Override in
* arch/mips/mach-xxx/kernel-entry-init.h when necessary.

9
arch/mips/include/asm/mach-ip28/spaces.h
View File

@ -11,11 +11,14 @@
#ifndef _ASM_MACH_IP28_SPACES_H
#define _ASM_MACH_IP28_SPACES_H
#define CAC_BASE 0xa800000000000000
#define CAC_BASE _AC(0xa800000000000000, UL)
#define HIGHMEM_START (~0UL)
#define HIGHMEM_START (~0UL)
#define PHYS_OFFSET _AC(0x20000000, UL)
#define PHYS_OFFSET _AC(0x20000000, UL)
#define UNCAC_BASE _AC(0xc0000000, UL) /* 0xa0000000 + PHYS_OFFSET */
#define IO_BASE UNCAC_BASE
#include <asm/mach-generic/spaces.h>

46
arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h
View File

@ -1,46 +0,0 @@
/*
* include/asm-mips/pmc-sierra/msp71xx/gpio.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* @author Patrick Glass <patrickglass@gmail.com>
*/
#ifndef __PMC_MSP71XX_GPIO_H
#define __PMC_MSP71XX_GPIO_H
/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */
#define ARCH_NR_GPIOS (28 + (3 * 8))
/* new generic GPIO API - see Documentation/gpio.txt */
#include <asm-generic/gpio.h>
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
/* Setup calls for the gpio and gpio extended */
extern void msp71xx_init_gpio(void);
extern void msp71xx_init_gpio_extended(void);
extern int msp71xx_set_output_drive(unsigned gpio, int value);
/* Custom output drive functionss */
static inline int gpio_set_output_drive(unsigned gpio, int value)
{
return msp71xx_set_output_drive(gpio, value);
}
/* IRQ's are not supported for gpio lines */
static inline int gpio_to_irq(unsigned gpio)
{
return -EINVAL;
}
static inline int irq_to_gpio(unsigned irq)
{
return -EINVAL;
}
#endif /* __PMC_MSP71XX_GPIO_H */

83
arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
View File

@ -1,83 +0,0 @@
/*
* This is a direct copy of the ev96100.h file, with a global
* search and replace. The numbers are the same.
*
* The reason I'm duplicating this is so that the 64120/96100
* defines won't be confusing in the source code.
*/
#ifndef __ASM_MIPS_GT64120_H
#define __ASM_MIPS_GT64120_H
/*
* This is the CPU physical memory map of PPMC Board:
*
* 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
* 0x1C000000-0x1C000000 - LED (CS0)
* 0x1C800000-0x1C800007 - UART 16550 port (CS1)
* 0x1F000000-0x1F000000 - MailBox (CS3)
* 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
*/
#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
#define WRPPMC_UART16550_BASE 0x1C800000
#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
#define WRPPMC_LED_BASE 0x1C000000
#define WRPPMC_MBOX_BASE 0x1F000000
#define WRPPMC_BOOTROM_BASE 0x1FC00000
#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
#define WRPPMC_UART16550_IRQ 6
#define WRPPMC_PCI_INTA_IRQ 3
/*
* PCI Bus I/O and Memory resources allocation
*
* NOTE: We only have PCI_0 hose interface
*/
#define GT_PCI_MEM_BASE 0x13000000UL
#define GT_PCI_MEM_SIZE 0x02000000UL
#define GT_PCI_IO_BASE 0x11000000UL
#define GT_PCI_IO_SIZE 0x02000000UL
/*
* PCI interrupts will come in on either the INTA or INTD interrupt lines,
* which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
* boards, they all either come in on IntD or they all come in on IntA, they
* aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
* "requested" interrupt numbers and go through the list whenever we get an
* IntA/D.
*
* Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
* INTD is 11.
*/
#define GT_TIMER 4
#define GT_INTA 2
#define GT_INTD 5
#ifndef __ASSEMBLY__
/*
* GT64120 internal register space base address
*/
extern unsigned long gt64120_base;
#define GT64120_BASE (gt64120_base)
/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
#undef WRPPMC_EARLY_DEBUG
#ifdef WRPPMC_EARLY_DEBUG
extern void wrppmc_led_on(int mask);
extern void wrppmc_led_off(int mask);
extern void wrppmc_early_printk(const char *fmt, ...);
#else
#define wrppmc_early_printk(fmt, ...) do {} while (0)
#endif /* WRPPMC_EARLY_DEBUG */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_MIPS_GT64120_H */

24
arch/mips/include/asm/mach-wrppmc/war.h
View File

@ -1,24 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H
#define __ASM_MIPS_MACH_WRPPMC_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */

6
arch/mips/include/asm/mips-boards/generic.h
View File

@ -23,12 +23,6 @@
#define ASCII_DISPLAY_WORD_BASE 0x1f000410
#define ASCII_DISPLAY_POS_BASE 0x1f000418
/*
* Reset register.
*/
#define SOFTRES_REG 0x1f000500
#define GORESET 0x42
/*
* Revision register.
*/

2
arch/mips/include/asm/mipsregs.h
View File

@ -596,7 +596,7 @@
#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
#define MIPS_CONF3_ISA_OE (_ULCAST_(3) << 16)
#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)

6
arch/mips/include/asm/mmu_context.h
View File

@ -28,11 +28,7 @@
#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
do { \
void (*tlbmiss_handler_setup_pgd)(unsigned long); \
extern u32 tlbmiss_handler_setup_pgd_array[16]; \
\
tlbmiss_handler_setup_pgd = \
(__typeof__(tlbmiss_handler_setup_pgd)) tlbmiss_handler_setup_pgd_array; \
extern void tlbmiss_handler_setup_pgd(unsigned long); \
tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
} while (0)

21
arch/mips/include/asm/netlogic/common.h
View File

@ -39,11 +39,17 @@
* Common SMP definitions
*/
#define RESET_VEC_PHYS 0x1fc00000
#define RESET_VEC_SIZE 8192 /* 8KB reset code and data */
#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
/* Offsets of parameters in the RESET_DATA_PHYS area */
#define BOOT_THREAD_MODE 0
#define BOOT_NMI_LOCK 4
#define BOOT_NMI_HANDLER 8
/* CPU ready flags for each CPU */
#define BOOT_CPU_READY 2048
#ifndef __ASSEMBLY__
#include <linux/cpumask.h>
#include <linux/spinlock.h>
@ -59,23 +65,32 @@ int nlm_wakeup_secondary_cpus(void);
void nlm_rmiboot_preboot(void);
void nlm_percpu_init(int hwcpuid);
static inline void *
nlm_get_boot_data(int offset)
{
return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset);
}
static inline void
nlm_set_nmi_handler(void *handler)
{
char *reset_data;
void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER);
reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
*(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
*(int64_t *)nmih = (long)handler;
}
/*
* Misc.
*/
void nlm_init_boot_cpu(void);
unsigned int nlm_get_cpu_frequency(void);
void nlm_node_init(int node);
extern struct plat_smp_ops nlm_smp_ops;
extern char nlm_reset_entry[], nlm_reset_entry_end[];
/* SWIOTLB */
extern struct dma_map_ops nlm_swiotlb_dma_ops;
extern unsigned int nlm_threads_per_core;
extern cpumask_t nlm_cpumask;

2
arch/mips/include/asm/netlogic/xlp-hal/pic.h
View File

@ -315,7 +315,7 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
{
uint64_t ipi;
ipi = (nmi << 31) | (irq << 20);
ipi = ((uint64_t)nmi << 31) | (irq << 20);
ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
}

1
arch/mips/include/asm/netlogic/xlp-hal/xlp.h
View File

@ -59,6 +59,7 @@ void xlp_wakeup_secondary_cpus(void);
void xlp_mmu_init(void);
void nlm_hal_init(void);
void *xlp_dt_init(void *fdtp);
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_NLM_XLP_H */

12
arch/mips/include/asm/netlogic/xlr/fmn.h
View File

@ -175,6 +175,10 @@
#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v)
#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v)
#define nlm_read_c2_status0() __read_32bit_c2_register($2, 0)
#define nlm_write_c2_status0(v) __write_32bit_c2_register($2, 0, v)
#define nlm_read_c2_status1() __read_32bit_c2_register($2, 1)
#define nlm_write_c2_status1(v) __write_32bit_c2_register($2, 1, v)
#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0)
#define nlm_read_c2_config() __read_32bit_c2_register($3, 0)
#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v)
@ -237,7 +241,7 @@ static inline void nlm_msgwait(unsigned int mask)
/*
* Disable interrupts and enable COP2 access
*/
static inline uint32_t nlm_cop2_enable(void)
static inline uint32_t nlm_cop2_enable_irqsave(void)
{
uint32_t sr = read_c0_status();
@ -245,7 +249,7 @@ static inline uint32_t nlm_cop2_enable(void)
return sr;
}
static inline void nlm_cop2_restore(uint32_t sr)
static inline void nlm_cop2_disable_irqrestore(uint32_t sr)
{
write_c0_status(sr);
}
@ -296,7 +300,7 @@ static inline int nlm_fmn_send(unsigned int size, unsigned int code,
*/
for (i = 0; i < 8; i++) {
nlm_msgsnd(dest);
status = nlm_read_c2_status(0);
status = nlm_read_c2_status0();
if ((status & 0x2) == 1)
pr_info("Send pending fail!\n");
if ((status & 0x4) == 0)
@ -316,7 +320,7 @@ static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
/* wait for load pending to clear */
do {
status = nlm_read_c2_status(1);
status = nlm_read_c2_status0();
} while ((status & 0x08) != 0);
/* receive error bits */

2
arch/mips/include/asm/octeon/cvmx-bootinfo.h
View File

@ -227,6 +227,7 @@ enum cvmx_board_types_enum {
* use any numbers in this range.
*/
CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
CVMX_BOARD_TYPE_UBNT_E100 = 20002,
CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
/* The remaining range is reserved for future use. */
@ -325,6 +326,7 @@ static inline const char *cvmx_board_type_to_string(enum
/* Customer private range */
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
}
return "Unsupported Board";

6
arch/mips/include/asm/page.h
View File

@ -205,10 +205,8 @@ extern int __virt_addr_valid(const volatile void *kaddr);
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \
PHYS_OFFSET)
#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \
PHYS_OFFSET)
#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
#include <asm-generic/memory_model.h>
#include <asm-generic/getorder.h>

1
arch/mips/include/asm/pci.h
View File

@ -52,7 +52,6 @@ struct pci_controller {
/*
* Used by boards to register their PCI busses before the actual scanning.
*/
extern struct pci_controller * alloc_pci_controller(void);
extern void register_pci_controller(struct pci_controller *hose);
/*

35
arch/mips/include/asm/processor.h
View File

@ -137,7 +137,7 @@ union mips_watch_reg_state {
struct mips3264_watch_reg_state mips3264;
};
#ifdef CONFIG_CPU_CAVIUM_OCTEON
#if defined(CONFIG_CPU_CAVIUM_OCTEON)
struct octeon_cop2_state {
/* DMFC2 rt, 0x0201 */
@ -182,13 +182,26 @@ struct octeon_cop2_state {
/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
unsigned long cop2_gfm_result[2];
};
#define INIT_OCTEON_COP2 {0,}
#define COP2_INIT \
.cp2 = {0,},
struct octeon_cvmseg_state {
unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
[cpu_dcache_line_size() / sizeof(unsigned long)];
};
#elif defined(CONFIG_CPU_XLP)
struct nlm_cop2_state {
u64 rx[4];
u64 tx[4];
u32 tx_msg_status;
u32 rx_msg_status;
};
#define COP2_INIT \
.cp2 = {{0}, {0}, 0, 0},
#else
#define COP2_INIT
#endif
typedef struct {
@ -231,8 +244,11 @@ struct thread_struct {
unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
unsigned long error_code;
#ifdef CONFIG_CPU_CAVIUM_OCTEON
struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
#endif
#ifdef CONFIG_CPU_XLP
struct nlm_cop2_state cp2;
#endif
struct mips_abi *abi;
};
@ -245,13 +261,6 @@ struct thread_struct {
#define FPAFF_INIT
#endif /* CONFIG_MIPS_MT_FPAFF */
#ifdef CONFIG_CPU_CAVIUM_OCTEON
#define OCTEON_INIT \
.cp2 = INIT_OCTEON_COP2,
#else
#define OCTEON_INIT
#endif /* CONFIG_CPU_CAVIUM_OCTEON */
#define INIT_THREAD { \
/* \
* Saved main processor registers \
@ -300,9 +309,9 @@ struct thread_struct {
.cp0_baduaddr = 0, \
.error_code = 0, \
/* \
* Cavium Octeon specifics (null if not Octeon) \
* Platform specific cop2 registers(null if no COP2) \
*/ \
OCTEON_INIT \
COP2_INIT \
}
struct task_struct;

29
arch/mips/include/asm/stackframe.h
View File

@ -69,6 +69,14 @@
LONG_S $24, PT_R24(sp)
#ifndef CONFIG_CPU_HAS_SMARTMIPS
LONG_S v1, PT_LO(sp)
#endif
#ifdef CONFIG_CPU_CAVIUM_OCTEON
/*
* The Octeon multiplier state is affected by general
* multiply instructions. It must be saved before and
* kernel code might corrupt it
*/
jal octeon_mult_save
#endif
.endm
@ -218,17 +226,8 @@
ori $28, sp, _THREAD_MASK
xori $28, _THREAD_MASK
#ifdef CONFIG_CPU_CAVIUM_OCTEON
.set mips64
pref 0, 0($28) /* Prefetch the current pointer */
pref 0, PT_R31(sp) /* Prefetch the $31(ra) */
/* The Octeon multiplier state is affected by general multiply
instructions. It must be saved before and kernel code might
corrupt it */
jal octeon_mult_save
LONG_L v1, 0($28) /* Load the current pointer */
/* Restore $31(ra) that was changed by the jal */
LONG_L ra, PT_R31(sp)
pref 0, 0(v1) /* Prefetch the current thread */
.set mips64
pref 0, 0($28) /* Prefetch the current pointer */
#endif
.set pop
.endm
@ -248,6 +247,10 @@
.endm
.macro RESTORE_TEMP
#ifdef CONFIG_CPU_CAVIUM_OCTEON
/* Restore the Octeon multiplier state */
jal octeon_mult_restore
#endif
#ifdef CONFIG_CPU_HAS_SMARTMIPS
LONG_L $24, PT_ACX(sp)
mtlhx $24
@ -360,10 +363,6 @@
DVPE 5 # dvpe a1
jal mips_ihb
#endif /* CONFIG_MIPS_MT_SMTC */
#ifdef CONFIG_CPU_CAVIUM_OCTEON
/* Restore the Octeon multiplier state */
jal octeon_mult_restore
#endif
mfc0 a0, CP0_STATUS
ori a0, STATMASK
xori a0, STATMASK

40
arch/mips/include/asm/stackprotector.h 100644
View File

@ -0,0 +1,40 @@
/*
* GCC stack protector support.
*
* (This is directly adopted from the ARM implementation)
*
* Stack protector works by putting predefined pattern at the start of
* the stack frame and verifying that it hasn't been overwritten when
* returning from the function. The pattern is called stack canary
* and gcc expects it to be defined by a global variable called
* "__stack_chk_guard" on MIPS. This unfortunately means that on SMP
* we cannot have a different canary value per task.
*/
#ifndef _ASM_STACKPROTECTOR_H
#define _ASM_STACKPROTECTOR_H 1
#include <linux/random.h>
#include <linux/version.h>
extern unsigned long __stack_chk_guard;
/*
* Initialize the stackprotector canary value.
*
* NOTE: this must only be called from functions that never return,
* and it must always be inlined.
*/
static __always_inline void boot_init_stack_canary(void)
{
unsigned long canary;
/* Try to get a semi random initial value. */
get_random_bytes(&canary, sizeof(canary));
canary ^= LINUX_VERSION_CODE;
current->stack_canary = canary;
__stack_chk_guard = current->stack_canary;
}
#endif /* _ASM_STACKPROTECTOR_H */

19
arch/mips/include/asm/switch_to.h
View File

@ -15,6 +15,7 @@
#include <asm/cpu-features.h>
#include <asm/watch.h>
#include <asm/dsp.h>
#include <asm/cop2.h>
struct task_struct;
@ -66,10 +67,18 @@ do { \
#define switch_to(prev, next, last) \
do { \
u32 __usedfpu; \
u32 __usedfpu, __c0_stat; \
__mips_mt_fpaff_switch_to(prev); \
if (cpu_has_dsp) \
__save_dsp(prev); \
if (cop2_present && (KSTK_STATUS(prev) & ST0_CU2)) { \
if (cop2_lazy_restore) \
KSTK_STATUS(prev) &= ~ST0_CU2; \
__c0_stat = read_c0_status(); \
write_c0_status(__c0_stat | ST0_CU2); \
cop2_save(&prev->thread.cp2); \
write_c0_status(__c0_stat & ~ST0_CU2); \
} \
__clear_software_ll_bit(); \
__usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \
(last) = resume(prev, next, task_thread_info(next), __usedfpu); \
@ -77,6 +86,14 @@ do { \
#define finish_arch_switch(prev) \
do { \
u32 __c0_stat; \
if (cop2_present && !cop2_lazy_restore && \
(KSTK_STATUS(current) & ST0_CU2)) { \
__c0_stat = read_c0_status(); \
write_c0_status(__c0_stat | ST0_CU2); \
cop2_restore(&current->thread.cp2); \
write_c0_status(__c0_stat & ~ST0_CU2); \
} \
if (cpu_has_dsp) \
__restore_dsp(current); \
if (cpu_has_userlocal) \

11
arch/mips/include/asm/thread_info.h
View File

@ -109,6 +109,7 @@ static inline struct thread_info *current_thread_info(void)
#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
#define TIF_NOHZ 19 /* in adaptive nohz mode */
#define TIF_FIXADE 20 /* Fix address errors in software */
#define TIF_LOGADE 21 /* Log address errors to syslog */
#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */
@ -124,6 +125,7 @@ static inline struct thread_info *current_thread_info(void)
#define _TIF_SECCOMP (1<<TIF_SECCOMP)
#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
#define _TIF_USEDFPU (1<<TIF_USEDFPU)
#define _TIF_NOHZ (1<<TIF_NOHZ)
#define _TIF_FIXADE (1<<TIF_FIXADE)
#define _TIF_LOGADE (1<<TIF_LOGADE)
#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)
@ -131,14 +133,19 @@ static inline struct thread_info *current_thread_info(void)
#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
_TIF_SYSCALL_AUDIT)
/* work to do in syscall_trace_leave() */
#define _TIF_WORK_SYSCALL_EXIT (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
_TIF_SYSCALL_AUDIT)
/* work to do on interrupt/exception return */
#define _TIF_WORK_MASK \
(_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
/* work to do on any return to u-space */
#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT)
#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \
_TIF_WORK_SYSCALL_EXIT)
#endif /* __KERNEL__ */

9
arch/mips/include/asm/xtalk/xtalk.h
View File

@ -47,6 +47,15 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t;
#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
#ifdef CONFIG_PCI
extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
#else
static inline int bridge_probe(nasid_t nasid, int widget, int masterwid)
{
return 0;
}
#endif
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_XTALK_XTALK_H */

16
arch/mips/include/uapi/asm/fcntl.h
View File

@ -5,9 +5,10 @@
*
* Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
*/
#ifndef _ASM_FCNTL_H
#define _ASM_FCNTL_H
#ifndef _UAPI_ASM_FCNTL_H
#define _UAPI_ASM_FCNTL_H
#include <asm/sgidefs.h>
#define O_APPEND 0x0008
#define O_DSYNC 0x0010 /* used to be O_SYNC, see below */
@ -55,14 +56,15 @@
* contain all the same fields as struct flock.
*/
#ifdef CONFIG_32BIT
#if _MIPS_SIM != _MIPS_SIM_ABI64
#include <linux/types.h>
struct flock {
short l_type;
short l_whence;
off_t l_start;
off_t l_len;
__kernel_off_t l_start;
__kernel_off_t l_len;
long l_sysid;
__kernel_pid_t l_pid;
long pad[4];
@ -70,8 +72,8 @@ struct flock {
#define HAVE_ARCH_STRUCT_FLOCK
#endif /* CONFIG_32BIT */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#include <asm-generic/fcntl.h>
#endif /* _ASM_FCNTL_H */
#endif /* _UAPI_ASM_FCNTL_H */

9
arch/mips/include/uapi/asm/inst.h
View File

@ -409,10 +409,11 @@ enum mm_32f_73_minor_op {
enum mm_16c_minor_op {
mm_lwm16_op = 0x04,
mm_swm16_op = 0x05,
mm_jr16_op = 0x18,
mm_jrc_op = 0x1a,
mm_jalr16_op = 0x1c,
mm_jalrs16_op = 0x1e,
mm_jr16_op = 0x0c,
mm_jrc_op = 0x0d,
mm_jalr16_op = 0x0e,
mm_jalrs16_op = 0x0f,
mm_jraddiusp_op = 0x18,
};
/*

12
arch/mips/include/uapi/asm/msgbuf.h
View File

@ -14,25 +14,25 @@
struct msqid64_ds {
struct ipc64_perm msg_perm;
#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
#if !defined(__mips64) && defined(__MIPSEB__)
unsigned long __unused1;
#endif
__kernel_time_t msg_stime; /* last msgsnd time */
#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
#if !defined(__mips64) && defined(__MIPSEL__)
unsigned long __unused1;
#endif
#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
#if !defined(__mips64) && defined(__MIPSEB__)
unsigned long __unused2;
#endif
__kernel_time_t msg_rtime; /* last msgrcv time */
#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
#if !defined(__mips64) && defined(__MIPSEL__)
unsigned long __unused2;
#endif
#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
#if !defined(__mips64) && defined(__MIPSEB__)
unsigned long __unused3;
#endif
__kernel_time_t msg_ctime; /* last change time */
#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
#if !defined(__mips64) && defined(__MIPSEL__)
unsigned long __unused3;
#endif
unsigned long msg_cbytes; /* current number of bytes on queue */

2
arch/mips/include/uapi/asm/resource.h
View File

@ -26,7 +26,7 @@
* but we keep the old value on MIPS32,
* for compatibility:
*/
#ifdef CONFIG_32BIT
#ifndef __mips64
# define RLIM_INFINITY 0x7fffffffUL
#endif

4
arch/mips/include/uapi/asm/siginfo.h
View File

@ -25,10 +25,10 @@ struct siginfo;
/*
* Careful to keep union _sifields from shifting ...
*/
#ifdef CONFIG_32BIT
#if __SIZEOF_LONG__ == 4
#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
#endif
#ifdef CONFIG_64BIT
#if __SIZEOF_LONG__ == 8
#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
#endif

12
arch/mips/include/uapi/asm/swab.h
View File

@ -13,7 +13,7 @@
#define __SWAB_64_THRU_32__
#ifdef CONFIG_CPU_MIPSR2
#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
{
@ -39,10 +39,10 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
#define __arch_swab32 __arch_swab32
/*
* Having already checked for CONFIG_CPU_MIPSR2, enable the
* optimized version for 64-bit kernel on r2 CPUs.
* Having already checked for MIPS R2, enable the optimized version for
* 64-bit kernel on r2 CPUs.
*/
#ifdef CONFIG_64BIT
#ifdef __mips64
static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
{
__asm__(
@ -54,6 +54,6 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
return x;
}
#define __arch_swab64 __arch_swab64
#endif /* CONFIG_64BIT */
#endif /* CONFIG_CPU_MIPSR2 */
#endif /* __mips64 */
#endif /* MIPS R2 or newer */
#endif /* _ASM_SWAB_H */

3
arch/mips/kernel/asm-offsets.c
View File

@ -82,6 +82,9 @@ void output_task_defines(void)
OFFSET(TASK_FLAGS, task_struct, flags);
OFFSET(TASK_MM, task_struct, mm);
OFFSET(TASK_PID, task_struct, pid);
#if defined(CONFIG_CC_STACKPROTECTOR)
OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
#endif
DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
BLANK();
}

1
arch/mips/kernel/branch.c
View File

@ -467,5 +467,4 @@ unaligned:
printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
force_sig(SIGBUS, current);
return -EFAULT;
}

5
arch/mips/kernel/cpu-bugs64.c
View File

@ -6,6 +6,7 @@
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/context_tracking.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ptrace.h>
@ -171,8 +172,12 @@ static volatile int daddi_ov __cpuinitdata;
asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
{
enum ctx_state prev_state;
prev_state = exception_enter();
daddi_ov = 1;
regs->cp0_epc += 4;
exception_exit(prev_state);
}
static inline void check_daddi(void)

12
arch/mips/kernel/cpu-probe.c
View File

@ -146,8 +146,7 @@ static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
case MIPS_CPU_ISA_IV:
c->isa_level |= MIPS_CPU_ISA_IV;
case MIPS_CPU_ISA_III:
c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II |
MIPS_CPU_ISA_III;
c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
break;
case MIPS_CPU_ISA_M32R2:
@ -156,8 +155,6 @@ static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
c->isa_level |= MIPS_CPU_ISA_M32R1;
case MIPS_CPU_ISA_II:
c->isa_level |= MIPS_CPU_ISA_II;
case MIPS_CPU_ISA_I:
c->isa_level |= MIPS_CPU_ISA_I;
break;
}
}
@ -272,9 +269,6 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
c->options |= MIPS_CPU_ULRI;
if (config3 & MIPS_CONF3_ISA)
c->options |= MIPS_CPU_MICROMIPS;
#ifdef CONFIG_CPU_MICROMIPS
write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE);
#endif
if (config3 & MIPS_CONF3_VZ)
c->ases |= MIPS_ASE_VZ;
@ -332,7 +326,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
case PRID_IMP_R2000:
c->cputype = CPU_R2000;
__cpu_name[cpu] = "R2000";
set_isa(c, MIPS_CPU_ISA_I);
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
MIPS_CPU_NOFPUEX;
if (__cpu_has_fpu())
@ -352,7 +345,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
c->cputype = CPU_R3000;
__cpu_name[cpu] = "R3000";
}
set_isa(c, MIPS_CPU_ISA_I);
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
MIPS_CPU_NOFPUEX;
if (__cpu_has_fpu())
@ -455,7 +447,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
break;
#endif
case PRID_IMP_TX39:
set_isa(c, MIPS_CPU_ISA_I);
c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
@ -959,6 +950,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
set_isa(c, MIPS_CPU_ISA_M64R1);
c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
}
c->kscratch_mask = 0xf;
}
#ifdef CONFIG_64BIT

39
arch/mips/kernel/head.S
View File

@ -27,45 +27,6 @@
#include <kernel-entry-init.h>
/*
* inputs are the text nasid in t1, data nasid in t2.
*/
.macro MAPPED_KERNEL_SETUP_TLB
#ifdef CONFIG_MAPPED_KERNEL
/*
* This needs to read the nasid - assume 0 for now.
* Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
* 0+DVG in tlblo_1.
*/
dli t0, 0xffffffffc0000000
dmtc0 t0, CP0_ENTRYHI
li t0, 0x1c000 # Offset of text into node memory
dsll t1, NASID_SHFT # Shift text nasid into place
dsll t2, NASID_SHFT # Same for data nasid
or t1, t1, t0 # Physical load address of kernel text
or t2, t2, t0 # Physical load address of kernel data
dsrl t1, 12 # 4K pfn
dsrl t2, 12 # 4K pfn
dsll t1, 6 # Get pfn into place
dsll t2, 6 # Get pfn into place
li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
or t0, t0, t1
mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
or t0, t0, t2
mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
mtc0 t0, CP0_PAGEMASK
li t0, 0 # KMAP_INX
mtc0 t0, CP0_INDEX
li t0, 1
mtc0 t0, CP0_WIRED
tlbwi
#else
mtc0 zero, CP0_WIRED
#endif
.endm
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using

15
arch/mips/kernel/irq-gic.c
View File

@ -219,16 +219,15 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
/* Assumption : cpumask refers to a single CPU */
spin_lock_irqsave(&gic_lock, flags);
for (;;) {
/* Re-route this IRQ */
GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
/* Update the pcpu_masks */
for (i = 0; i < NR_CPUS; i++)
clear_bit(irq, pcpu_masks[i].pcpu_mask);
set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
/* Re-route this IRQ */
GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
/* Update the pcpu_masks */
for (i = 0; i < NR_CPUS; i++)
clear_bit(irq, pcpu_masks[i].pcpu_mask);
set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
}
cpumask_copy(d->affinity, cpumask);
spin_unlock_irqrestore(&gic_lock, flags);

4
arch/mips/kernel/mcount.S
View File

@ -168,14 +168,10 @@ NESTED(ftrace_graph_caller, PT_SIZE, ra)
#endif
/* arg3: Get frame pointer of current stack */
#ifdef CONFIG_FRAME_POINTER
move a2, fp
#else /* ! CONFIG_FRAME_POINTER */
#ifdef CONFIG_64BIT
PTR_LA a2, PT_SIZE(sp)
#else
PTR_LA a2, (PT_SIZE+8)(sp)
#endif
#endif
jal prepare_ftrace_return

34
arch/mips/kernel/octeon_switch.S
View File

@ -40,33 +40,6 @@
cpu_save_nonscratch a0
LONG_S ra, THREAD_REG31(a0)
/* check if we need to save COP2 registers */
PTR_L t2, TASK_THREAD_INFO(a0)
LONG_L t0, ST_OFF(t2)
bbit0 t0, 30, 1f
/* Disable COP2 in the stored process state */
li t1, ST0_CU2
xor t0, t1
LONG_S t0, ST_OFF(t2)
/* Enable COP2 so we can save it */
mfc0 t0, CP0_STATUS
or t0, t1
mtc0 t0, CP0_STATUS
/* Save COP2 */
daddu a0, THREAD_CP2
jal octeon_cop2_save
dsubu a0, THREAD_CP2
/* Disable COP2 now that we are done */
mfc0 t0, CP0_STATUS
li t1, ST0_CU2
xor t0, t1
mtc0 t0, CP0_STATUS
1:
#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
/* Check if we need to store CVMSEG state */
mfc0 t0, $11,7 /* CvmMemCtl */
@ -98,6 +71,13 @@
mtc0 t0, $11,7 /* CvmMemCtl */
#endif
3:
#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
PTR_L t8, __stack_chk_guard
LONG_L t9, TASK_STACK_CANARY(a1)
LONG_S t9, 0(t8)
#endif
/*
* The order of restoring the registers takes care of the race
* updating $28, $29 and kernelsp without disabling ints.

4
arch/mips/kernel/proc.c
View File

@ -66,9 +66,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "]\n");
}
if (cpu_has_mips_r) {
seq_printf(m, "isa\t\t\t:");
if (cpu_has_mips_1)
seq_printf(m, "%s", " mips1");
seq_printf(m, "isa\t\t\t: mips1");
if (cpu_has_mips_2)
seq_printf(m, "%s", " mips2");
if (cpu_has_mips_3)

9
arch/mips/kernel/process.c
View File

@ -201,9 +201,12 @@ int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpr)
return 1;
}
/*
*
*/
#ifdef CONFIG_CC_STACKPROTECTOR
#include <linux/stackprotector.h>
unsigned long __stack_chk_guard __read_mostly;
EXPORT_SYMBOL(__stack_chk_guard);
#endif
struct mips_frame_info {
void *func;
unsigned long func_size;

2
arch/mips/kernel/prom.c
View File

@ -30,7 +30,7 @@ __init void mips_set_machine_name(const char *name)
if (name == NULL)
return;
strncpy(mips_machine_name, name, sizeof(mips_machine_name));
strlcpy(mips_machine_name, name, sizeof(mips_machine_name));
pr_info("MIPS: machine is %s\n", mips_get_machine_name());
}

12
arch/mips/kernel/ptrace.c
View File

@ -15,6 +15,7 @@
* binaries.
*/
#include <linux/compiler.h>
#include <linux/context_tracking.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
@ -534,6 +535,8 @@ static inline int audit_arch(void)
*/
asmlinkage void syscall_trace_enter(struct pt_regs *regs)
{
user_exit();
/* do the secure computing check first */
secure_computing_strict(regs->regs[2]);
@ -570,6 +573,13 @@ out:
*/
asmlinkage void syscall_trace_leave(struct pt_regs *regs)
{
/*
* We may come here right after calling schedule_user()
* or do_notify_resume(), in which case we can be in RCU
* user mode.
*/
user_exit();
audit_syscall_exit(regs);
if (!(current->ptrace & PT_PTRACED))
@ -592,4 +602,6 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs)
send_sig(current->exit_code, current, 1);
current->exit_code = 0;
}
user_enter();
}

7
arch/mips/kernel/r2300_switch.S
View File

@ -65,6 +65,13 @@ LEAF(resume)
fpu_save_single a0, t0 # clobbers t0
1:
#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
PTR_L t8, __stack_chk_guard
LONG_L t9, TASK_STACK_CANARY(a1)
LONG_S t9, 0(t8)
#endif
/*
* The order of restoring the registers takes care of the race
* updating $28, $29 and kernelsp without disabling ints.

6
arch/mips/kernel/r4k_switch.S
View File

@ -68,6 +68,12 @@
# clobbers t1
1:
#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
PTR_L t8, __stack_chk_guard
LONG_L t9, TASK_STACK_CANARY(a1)
LONG_S t9, 0(t8)
#endif
/*
* The order of restoring the registers takes care of the race
* updating $28, $29 and kernelsp without disabling ints.

1
arch/mips/kernel/rtlx.c
View File

@ -437,7 +437,6 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
size_t count, loff_t * ppos)
{
int minor = iminor(file_inode(file));
struct rtlx_channel *rt = &rtlx->channel[minor];
/* any space left... */
if (!rtlx_write_poll(minor)) {

2
arch/mips/kernel/scall32-o32.S
View File

@ -52,7 +52,7 @@ NESTED(handle_sys, PT_SIZE, sp)
stack_done:
lw t0, TI_FLAGS($28) # syscall tracing enabled?
li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
li t1, _TIF_WORK_SYSCALL_ENTRY
and t0, t1
bnez t0, syscall_trace_entry # -> yes

2
arch/mips/kernel/scall64-64.S
View File

@ -54,7 +54,7 @@ NESTED(handle_sys64, PT_SIZE, sp)
sd a3, PT_R26(sp) # save a3 for syscall restarting
li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
li t1, _TIF_WORK_SYSCALL_ENTRY
LONG_L t0, TI_FLAGS($28) # syscall tracing enabled?
and t0, t1, t0
bnez t0, syscall_trace_entry

2
arch/mips/kernel/scall64-n32.S
View File

@ -47,7 +47,7 @@ NESTED(handle_sysn32, PT_SIZE, sp)
sd a3, PT_R26(sp) # save a3 for syscall restarting
li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
li t1, _TIF_WORK_SYSCALL_ENTRY
LONG_L t0, TI_FLAGS($28) # syscall tracing enabled?
and t0, t1, t0
bnez t0, n32_syscall_trace_entry

2
arch/mips/kernel/scall64-o32.S
View File

@ -81,7 +81,7 @@ NESTED(handle_sys, PT_SIZE, sp)
PTR 4b, bad_stack
.previous
li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
li t1, _TIF_WORK_SYSCALL_ENTRY
LONG_L t0, TI_FLAGS($28) # syscall tracing enabled?
and t0, t1, t0
bnez t0, trace_a_syscall

5
arch/mips/kernel/signal.c
View File

@ -8,6 +8,7 @@
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
#include <linux/cache.h>
#include <linux/context_tracking.h>
#include <linux/irqflags.h>
#include <linux/sched.h>
#include <linux/mm.h>
@ -573,6 +574,8 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
{
local_irq_enable();
user_exit();
/* deal with pending signal delivery */
if (thread_info_flags & _TIF_SIGPENDING)
do_signal(regs);
@ -581,6 +584,8 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
clear_thread_flag(TIF_NOTIFY_RESUME);
tracehook_notify_resume(regs);
}
user_enter();
}
#ifdef CONFIG_SMP

29
arch/mips/kernel/smp-bmips.c
View File

@ -63,7 +63,7 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
static void __init bmips_smp_setup(void)
{
int i;
int i, cpu = 1, boot_cpu = 0;
#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
/* arbitration priority */
@ -72,13 +72,22 @@ static void __init bmips_smp_setup(void)
/* NBK and weak order flags */
set_c0_brcm_config_0(0x30000);
/* Find out if we are running on TP0 or TP1 */
boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
/*
* MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
* MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
* MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
*
* If booting from TP1, leave the existing CMT interrupt routing
* such that TP0 responds to SW1 and TP1 responds to SW0.
*/
change_c0_brcm_cmt_intr(0xf8018000,
(0x02 << 27) | (0x03 << 15));
if (boot_cpu == 0)
change_c0_brcm_cmt_intr(0xf8018000,
(0x02 << 27) | (0x03 << 15));
else
change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
/* single core, 2 threads (2 pipelines) */
max_cpus = 2;
@ -106,9 +115,15 @@ static void __init bmips_smp_setup(void)
if (!board_ebase_setup)
board_ebase_setup = &bmips_ebase_setup;
__cpu_number_map[boot_cpu] = 0;
__cpu_logical_map[0] = boot_cpu;
for (i = 0; i < max_cpus; i++) {
__cpu_number_map[i] = 1;
__cpu_logical_map[i] = 1;
if (i != boot_cpu) {
__cpu_number_map[i] = cpu;
__cpu_logical_map[cpu] = i;
cpu++;
}
set_cpu_possible(i, 1);
set_cpu_present(i, 1);
}
@ -157,7 +172,9 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
bmips_send_ipi_single(cpu, 0);
else {
#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
set_c0_brcm_cmt_ctrl(0x01);
/* Reset slave TP1 if booting from TP0 */
if (cpu_logical_map(cpu) == 0)
set_c0_brcm_cmt_ctrl(0x01);
#elif defined(CONFIG_CPU_BMIPS5000)
if (cpu & 0x01)
write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));

104
arch/mips/kernel/traps.c
View File

@ -13,6 +13,7 @@
*/
#include <linux/bug.h>
#include <linux/compiler.h>
#include <linux/context_tracking.h>
#include <linux/kexec.h>
#include <linux/init.h>
#include <linux/kernel.h>
@ -264,7 +265,7 @@ static void __show_regs(const struct pt_regs *regs)
printk("Status: %08x ", (uint32_t) regs->cp0_status);
if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
if (cpu_has_3kex) {
if (regs->cp0_status & ST0_KUO)
printk("KUo ");
if (regs->cp0_status & ST0_IEO)
@ -277,7 +278,7 @@ static void __show_regs(const struct pt_regs *regs)
printk("KUc ");
if (regs->cp0_status & ST0_IEC)
printk("IEc ");
} else {
} else if (cpu_has_4kex) {
if (regs->cp0_status & ST0_KX)
printk("KX ");
if (regs->cp0_status & ST0_SX)
@ -423,7 +424,9 @@ asmlinkage void do_be(struct pt_regs *regs)
const struct exception_table_entry *fixup = NULL;
int data = regs->cp0_cause & 4;
int action = MIPS_BE_FATAL;
enum ctx_state prev_state;
prev_state = exception_enter();
/* XXX For now. Fixme, this searches the wrong table ... */
if (data && !user_mode(regs))
fixup = search_dbe_tables(exception_epc(regs));
@ -436,11 +439,11 @@ asmlinkage void do_be(struct pt_regs *regs)
switch (action) {
case MIPS_BE_DISCARD:
return;
goto out;
case MIPS_BE_FIXUP:
if (fixup) {
regs->cp0_epc = fixup->nextinsn;
return;
goto out;
}
break;
default:
@ -455,10 +458,13 @@ asmlinkage void do_be(struct pt_regs *regs)
field, regs->cp0_epc, field, regs->regs[31]);
if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
== NOTIFY_STOP)
return;
goto out;
die_if_kernel("Oops", regs);
force_sig(SIGBUS, current);
out:
exception_exit(prev_state);
}
/*
@ -673,8 +679,10 @@ static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
asmlinkage void do_ov(struct pt_regs *regs)
{
enum ctx_state prev_state;
siginfo_t info;
prev_state = exception_enter();
die_if_kernel("Integer overflow", regs);
info.si_code = FPE_INTOVF;
@ -682,6 +690,7 @@ asmlinkage void do_ov(struct pt_regs *regs)
info.si_errno = 0;
info.si_addr = (void __user *) regs->cp0_epc;
force_sig_info(SIGFPE, &info, current);
exception_exit(prev_state);
}
int process_fpemu_return(int sig, void __user *fault_addr)
@ -713,11 +722,13 @@ int process_fpemu_return(int sig, void __user *fault_addr)
*/
asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
{
enum ctx_state prev_state;
siginfo_t info = {0};
prev_state = exception_enter();
if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
== NOTIFY_STOP)
return;
goto out;
die_if_kernel("FP exception in kernel code", regs);
if (fcr31 & FPU_CSR_UNI_X) {
@ -753,7 +764,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
/* If something went wrong, signal */
process_fpemu_return(sig, fault_addr);
return;
goto out;
} else if (fcr31 & FPU_CSR_INV_X)
info.si_code = FPE_FLTINV;
else if (fcr31 & FPU_CSR_DIV_X)
@ -770,6 +781,9 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
info.si_errno = 0;
info.si_addr = (void __user *) regs->cp0_epc;
force_sig_info(SIGFPE, &info, current);
out:
exception_exit(prev_state);
}
static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
@ -835,9 +849,11 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
asmlinkage void do_bp(struct pt_regs *regs)
{
unsigned int opcode, bcode;
enum ctx_state prev_state;
unsigned long epc;
u16 instr[2];
prev_state = exception_enter();
if (get_isa16_mode(regs->cp0_epc)) {
/* Calculate EPC. */
epc = exception_epc(regs);
@ -852,7 +868,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
goto out_sigsegv;
bcode = (instr[0] >> 6) & 0x3f;
do_trap_or_bp(regs, bcode, "Break");
return;
goto out;
}
} else {
if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
@ -876,12 +892,12 @@ asmlinkage void do_bp(struct pt_regs *regs)
switch (bcode) {
case BRK_KPROBE_BP:
if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
return;
goto out;
else
break;
case BRK_KPROBE_SSTEPBP:
if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
return;
goto out;
else
break;
default:
@ -889,18 +905,24 @@ asmlinkage void do_bp(struct pt_regs *regs)
}
do_trap_or_bp(regs, bcode, "Break");
out:
exception_exit(prev_state);
return;
out_sigsegv:
force_sig(SIGSEGV, current);
goto out;
}
asmlinkage void do_tr(struct pt_regs *regs)
{
u32 opcode, tcode = 0;
enum ctx_state prev_state;
u16 instr[2];
unsigned long epc = msk_isa16_mode(exception_epc(regs));
prev_state = exception_enter();
if (get_isa16_mode(regs->cp0_epc)) {
if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
__get_user(instr[1], (u16 __user *)(epc + 2)))
@ -918,10 +940,14 @@ asmlinkage void do_tr(struct pt_regs *regs)
}
do_trap_or_bp(regs, tcode, "Trap");
out:
exception_exit(prev_state);
return;
out_sigsegv:
force_sig(SIGSEGV, current);
goto out;
}
asmlinkage void do_ri(struct pt_regs *regs)
@ -929,17 +955,19 @@ asmlinkage void do_ri(struct pt_regs *regs)
unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
unsigned long old_epc = regs->cp0_epc;
unsigned long old31 = regs->regs[31];
enum ctx_state prev_state;
unsigned int opcode = 0;
int status = -1;
prev_state = exception_enter();
if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
== NOTIFY_STOP)
return;
goto out;
die_if_kernel("Reserved instruction in kernel code", regs);
if (unlikely(compute_return_epc(regs) < 0))
return;
goto out;
if (get_isa16_mode(regs->cp0_epc)) {
unsigned short mmop[2] = { 0 };
@ -974,6 +1002,9 @@ asmlinkage void do_ri(struct pt_regs *regs)
regs->regs[31] = old31;
force_sig(status, current);
}
out:
exception_exit(prev_state);
}
/*
@ -1025,21 +1056,16 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
{
struct pt_regs *regs = data;
switch (action) {
default:
die_if_kernel("Unhandled kernel unaligned access or invalid "
die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
"instruction", regs);
/* Fall through */
case CU2_EXCEPTION:
force_sig(SIGILL, current);
}
force_sig(SIGILL, current);
return NOTIFY_OK;
}
asmlinkage void do_cpu(struct pt_regs *regs)
{
enum ctx_state prev_state;
unsigned int __user *epc;
unsigned long old_epc, old31;
unsigned int opcode;
@ -1047,10 +1073,12 @@ asmlinkage void do_cpu(struct pt_regs *regs)
int status;
unsigned long __maybe_unused flags;
die_if_kernel("do_cpu invoked from kernel context!", regs);
prev_state = exception_enter();
cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
if (cpid != 2)
die_if_kernel("do_cpu invoked from kernel context!", regs);
switch (cpid) {
case 0:
epc = (unsigned int __user *)exception_epc(regs);
@ -1060,7 +1088,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
status = -1;
if (unlikely(compute_return_epc(regs) < 0))
return;
goto out;
if (get_isa16_mode(regs->cp0_epc)) {
unsigned short mmop[2] = { 0 };
@ -1093,7 +1121,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
force_sig(status, current);
}
return;
goto out;
case 3:
/*
@ -1131,19 +1159,26 @@ asmlinkage void do_cpu(struct pt_regs *regs)
mt_ase_fp_affinity();
}
return;
goto out;
case 2:
raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
return;
goto out;
}
force_sig(SIGILL, current);
out:
exception_exit(prev_state);
}
asmlinkage void do_mdmx(struct pt_regs *regs)
{
enum ctx_state prev_state;
prev_state = exception_enter();
force_sig(SIGILL, current);
exception_exit(prev_state);
}
/*
@ -1151,8 +1186,10 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
*/
asmlinkage void do_watch(struct pt_regs *regs)
{
enum ctx_state prev_state;
u32 cause;
prev_state = exception_enter();
/*
* Clear WP (bit 22) bit of cause register so we don't loop
* forever.
@ -1174,13 +1211,16 @@ asmlinkage void do_watch(struct pt_regs *regs)
mips_clear_watch_registers();
local_irq_enable();
}
exception_exit(prev_state);
}
asmlinkage void do_mcheck(struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
int multi_match = regs->cp0_status & ST0_TS;
enum ctx_state prev_state;
prev_state = exception_enter();
show_regs(regs);
if (multi_match) {
@ -1202,6 +1242,7 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
panic("Caught Machine Check exception - %scaused by multiple "
"matching entries in the TLB.",
(multi_match) ? "" : "not ");
exception_exit(prev_state);
}
asmlinkage void do_mt(struct pt_regs *regs)
@ -1627,7 +1668,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
}
extern void tlb_init(void);
extern void flush_tlb_handlers(void);
/*
* Timer interrupt
@ -1837,6 +1877,15 @@ void __init trap_init(void)
ebase += (read_c0_ebase() & 0x3ffff000);
}
if (cpu_has_mmips) {
unsigned int config3 = read_c0_config3();
if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
else
write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
}
if (board_ebase_setup)
board_ebase_setup();
per_cpu_trap_init(true);
@ -1956,7 +2005,6 @@ void __init trap_init(void)
set_handler(0x080, &except_vec3_generic, 0x80);
local_flush_icache_range(ebase, ebase + 0x400);
flush_tlb_handlers();
sort_extable(__start___dbe_table, __stop___dbe_table);

8
arch/mips/kernel/unaligned.c
View File

@ -72,6 +72,7 @@
* A store crossing a page boundary might be executed only partially.
* Undo the partial store in this case.
*/
#include <linux/context_tracking.h>
#include <linux/mm.h>
#include <linux/signal.h>
#include <linux/smp.h>
@ -684,7 +685,8 @@ const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
/* Recode table from 16-bit STORE register notation to 32-bit GPR. */
const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
void emulate_load_store_microMIPS(struct pt_regs *regs, void __user * addr)
static void emulate_load_store_microMIPS(struct pt_regs *regs,
void __user *addr)
{
unsigned long value;
unsigned int res;
@ -1548,11 +1550,14 @@ sigill:
("Unhandled kernel unaligned access or invalid instruction", regs);
force_sig(SIGILL, current);
}
asmlinkage void do_ade(struct pt_regs *regs)
{
enum ctx_state prev_state;
unsigned int __user *pc;
mm_segment_t seg;
prev_state = exception_enter();
perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
1, regs, regs->cp0_badvaddr);
/*
@ -1628,6 +1633,7 @@ sigbus:
/*
* XXX On return from the signal handler we should advance the epc
*/
exception_exit(prev_state);
}
#ifdef CONFIG_DEBUG_FS

8
arch/mips/kernel/watch.c
View File

@ -111,6 +111,7 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
* disable the register.
*/
write_c0_watchlo0(7);
back_to_back_c0_hazard();
t = read_c0_watchlo0();
write_c0_watchlo0(0);
c->watch_reg_masks[0] = t & 7;
@ -121,12 +122,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
c->watch_reg_use_cnt = 1;
t = read_c0_watchhi0();
write_c0_watchhi0(t | 0xff8);
back_to_back_c0_hazard();
t = read_c0_watchhi0();
c->watch_reg_masks[0] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo1(7);
back_to_back_c0_hazard();
t = read_c0_watchlo1();
write_c0_watchlo1(0);
c->watch_reg_masks[1] = t & 7;
@ -135,12 +138,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
c->watch_reg_use_cnt = 2;
t = read_c0_watchhi1();
write_c0_watchhi1(t | 0xff8);
back_to_back_c0_hazard();
t = read_c0_watchhi1();
c->watch_reg_masks[1] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo2(7);
back_to_back_c0_hazard();
t = read_c0_watchlo2();
write_c0_watchlo2(0);
c->watch_reg_masks[2] = t & 7;
@ -149,12 +154,14 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
c->watch_reg_use_cnt = 3;
t = read_c0_watchhi2();
write_c0_watchhi2(t | 0xff8);
back_to_back_c0_hazard();
t = read_c0_watchhi2();
c->watch_reg_masks[2] |= (t & 0xff8);
if ((t & 0x80000000) == 0)
return;
write_c0_watchlo3(7);
back_to_back_c0_hazard();
t = read_c0_watchlo3();
write_c0_watchlo3(0);
c->watch_reg_masks[3] = t & 7;
@ -163,6 +170,7 @@ __cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
c->watch_reg_use_cnt = 4;
t = read_c0_watchhi3();
write_c0_watchhi3(t | 0xff8);
back_to_back_c0_hazard();
t = read_c0_watchhi3();
c->watch_reg_masks[3] |= (t & 0xff8);
if ((t & 0x80000000) == 0)

2
arch/mips/lantiq/prom.c
View File

@ -112,7 +112,7 @@ int __init plat_of_setup(void)
if (!of_have_populated_dt())
panic("device tree not present");
strncpy(of_ids[0].compatible, soc_info.compatible,
strlcpy(of_ids[0].compatible, soc_info.compatible,
sizeof(of_ids[0].compatible));
strncpy(of_ids[1].compatible, "simple-bus",
sizeof(of_ids[1].compatible));

Some files were not shown because too many files have changed in this diff Show More