ARM: at91/pm_slowclock: remove clocks which are already stopped when entering slow clock mode
Assume USB PLL and PLL B are already stopped before entering sleep mode. Removed PLL B from slow clock code, all drivers are supposed to properly unprepare clocks. Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com> Acked-by: Wenyou.Yang <wenyou.yang@atmel.com> [nicolas.ferre@atmel.com: remove the warning printed in pm.c] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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@ -50,15 +50,6 @@ tmp2 .req r5
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beq 1b
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.endm
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/*
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* Wait until PLLB has locked.
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*/
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.macro wait_pllblock
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1: ldr tmp1, [pmc, #AT91_PMC_SR]
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tst tmp1, #AT91_PMC_LOCKB
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beq 1b
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.endm
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.text
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.arm
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@ -176,13 +167,6 @@ sdr_sr_done:
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orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
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str tmp1, [pmc, #AT91_CKGR_PLLAR]
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/* Save PLLB setting and disable it */
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ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
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str tmp1, .saved_pllbr
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mov tmp1, #AT91_PMC_PLLCOUNT
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str tmp1, [pmc, #AT91_CKGR_PLLBR]
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/* Turn off the main oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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bic tmp1, tmp1, #AT91_PMC_MOSCEN
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@ -200,18 +184,6 @@ sdr_sr_done:
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wait_moscrdy
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/* Restore PLLB setting */
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ldr tmp1, .saved_pllbr
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str tmp1, [pmc, #AT91_CKGR_PLLBR]
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tst tmp1, #(AT91_PMC_MUL & 0xff0000)
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bne 1f
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tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
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beq 2f
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1:
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wait_pllblock
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2:
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/* Restore PLLA setting */
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ldr tmp1, .saved_pllar
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str tmp1, [pmc, #AT91_CKGR_PLLAR]
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@ -279,9 +251,6 @@ ram_restored:
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.saved_pllar:
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.word 0
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.saved_pllbr:
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.word 0
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.saved_sam9_lpr:
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.word 0
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