PCI: initialize and release SR-IOV capability
If a device has the SR-IOV capability, initialize it (set the ARI Capable Hierarchy in the lowest numbered PF if necessary; calculate the System Page Size for the VF MMIO, probe the VF Offset, Stride and BARs). A lock for the VF bus allocation is also initialized if a PF is the lowest numbered PF. Reviewed-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>hifive-unleashed-5.1
Yu Zhao
Jesse Barnes
parent
8293b0f629
commit
d1b054da8f
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@ -59,3 +59,13 @@ config HT_IRQ
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This allows native hypertransport devices to use interrupts.
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If unsure say Y.
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config PCI_IOV
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bool "PCI IOV support"
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depends on PCI
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help
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I/O Virtualization is a PCI feature supported by some devices
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which allows them to create virtual devices which share their
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physical resources.
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If unsure, say N.
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@ -29,6 +29,8 @@ obj-$(CONFIG_DMAR) += dmar.o iova.o intel-iommu.o
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obj-$(CONFIG_INTR_REMAP) += dmar.o intr_remapping.o
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obj-$(CONFIG_PCI_IOV) += iov.o
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#
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# Some architectures use the generic PCI setup functions
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#
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@ -0,0 +1,182 @@
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/*
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* drivers/pci/iov.c
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*
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* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
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*
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* PCI Express I/O Virtualization (IOV) support.
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* Single Root IOV 1.0
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*/
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#include <linux/pci.h>
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#include <linux/mutex.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include "pci.h"
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static int sriov_init(struct pci_dev *dev, int pos)
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{
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int i;
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int rc;
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int nres;
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u32 pgsz;
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u16 ctrl, total, offset, stride;
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struct pci_sriov *iov;
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struct resource *res;
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struct pci_dev *pdev;
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if (dev->pcie_type != PCI_EXP_TYPE_RC_END &&
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dev->pcie_type != PCI_EXP_TYPE_ENDPOINT)
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return -ENODEV;
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pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
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if (ctrl & PCI_SRIOV_CTRL_VFE) {
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pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, 0);
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ssleep(1);
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}
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pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &total);
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if (!total)
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return 0;
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ctrl = 0;
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list_for_each_entry(pdev, &dev->bus->devices, bus_list)
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if (pdev->is_physfn)
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goto found;
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pdev = NULL;
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if (pci_ari_enabled(dev->bus))
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ctrl |= PCI_SRIOV_CTRL_ARI;
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found:
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pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, ctrl);
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pci_write_config_word(dev, pos + PCI_SRIOV_NUM_VF, total);
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pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
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pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
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if (!offset || (total > 1 && !stride))
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return -EIO;
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pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &pgsz);
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i = PAGE_SHIFT > 12 ? PAGE_SHIFT - 12 : 0;
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pgsz &= ~((1 << i) - 1);
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if (!pgsz)
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return -EIO;
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pgsz &= ~(pgsz - 1);
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pci_write_config_dword(dev, pos + PCI_SRIOV_SYS_PGSIZE, pgsz);
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nres = 0;
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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res = dev->resource + PCI_IOV_RESOURCES + i;
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i += __pci_read_base(dev, pci_bar_unknown, res,
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pos + PCI_SRIOV_BAR + i * 4);
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if (!res->flags)
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continue;
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if (resource_size(res) & (PAGE_SIZE - 1)) {
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rc = -EIO;
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goto failed;
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}
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res->end = res->start + resource_size(res) * total - 1;
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nres++;
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}
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iov = kzalloc(sizeof(*iov), GFP_KERNEL);
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if (!iov) {
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rc = -ENOMEM;
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goto failed;
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}
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iov->pos = pos;
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iov->nres = nres;
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iov->ctrl = ctrl;
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iov->total = total;
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iov->offset = offset;
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iov->stride = stride;
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iov->pgsz = pgsz;
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iov->self = dev;
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pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
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pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
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if (pdev)
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iov->dev = pci_dev_get(pdev);
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else {
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iov->dev = dev;
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mutex_init(&iov->lock);
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}
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dev->sriov = iov;
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dev->is_physfn = 1;
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return 0;
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failed:
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
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res = dev->resource + PCI_IOV_RESOURCES + i;
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res->flags = 0;
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}
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return rc;
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}
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static void sriov_release(struct pci_dev *dev)
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{
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if (dev == dev->sriov->dev)
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mutex_destroy(&dev->sriov->lock);
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else
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pci_dev_put(dev->sriov->dev);
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kfree(dev->sriov);
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dev->sriov = NULL;
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}
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/**
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* pci_iov_init - initialize the IOV capability
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* @dev: the PCI device
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*
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* Returns 0 on success, or negative on failure.
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*/
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int pci_iov_init(struct pci_dev *dev)
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{
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int pos;
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if (!dev->is_pcie)
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return -ENODEV;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
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if (pos)
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return sriov_init(dev, pos);
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return -ENODEV;
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}
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/**
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* pci_iov_release - release resources used by the IOV capability
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* @dev: the PCI device
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*/
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void pci_iov_release(struct pci_dev *dev)
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{
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if (dev->is_physfn)
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sriov_release(dev);
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}
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/**
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* pci_iov_resource_bar - get position of the SR-IOV BAR
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* @dev: the PCI device
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* @resno: the resource number
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* @type: the BAR type to be filled in
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*
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* Returns position of the BAR encapsulated in the SR-IOV capability.
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*/
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int pci_iov_resource_bar(struct pci_dev *dev, int resno,
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enum pci_bar_type *type)
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{
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if (resno < PCI_IOV_RESOURCES || resno > PCI_IOV_RESOURCE_END)
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return 0;
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BUG_ON(!dev->is_physfn);
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*type = pci_bar_unknown;
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return dev->sriov->pos + PCI_SRIOV_BAR +
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4 * (resno - PCI_IOV_RESOURCES);
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}
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@ -2360,12 +2360,19 @@ int pci_select_bars(struct pci_dev *dev, unsigned long flags)
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*/
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int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
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{
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int reg;
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if (resno < PCI_ROM_RESOURCE) {
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*type = pci_bar_unknown;
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return PCI_BASE_ADDRESS_0 + 4 * resno;
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} else if (resno == PCI_ROM_RESOURCE) {
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*type = pci_bar_mem32;
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return dev->rom_base_reg;
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} else if (resno < PCI_BRIDGE_RESOURCES) {
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/* device specific resource */
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reg = pci_iov_resource_bar(dev, resno, type);
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if (reg)
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return reg;
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}
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dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno);
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@ -201,4 +201,41 @@ resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
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extern void pci_disable_bridge_window(struct pci_dev *dev);
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#endif
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/* Single Root I/O Virtualization */
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struct pci_sriov {
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int pos; /* capability position */
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int nres; /* number of resources */
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u32 cap; /* SR-IOV Capabilities */
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u16 ctrl; /* SR-IOV Control */
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u16 total; /* total VFs associated with the PF */
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u16 offset; /* first VF Routing ID offset */
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u16 stride; /* following VF stride */
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u32 pgsz; /* page size for BAR alignment */
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u8 link; /* Function Dependency Link */
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struct pci_dev *dev; /* lowest numbered PF */
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struct pci_dev *self; /* this PF */
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struct mutex lock; /* lock for VF bus */
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};
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#ifdef CONFIG_PCI_IOV
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extern int pci_iov_init(struct pci_dev *dev);
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extern void pci_iov_release(struct pci_dev *dev);
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extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
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enum pci_bar_type *type);
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#else
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static inline int pci_iov_init(struct pci_dev *dev)
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{
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return -ENODEV;
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}
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static inline void pci_iov_release(struct pci_dev *dev)
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{
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}
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static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
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enum pci_bar_type *type)
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{
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return 0;
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}
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#endif /* CONFIG_PCI_IOV */
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#endif /* DRIVERS_PCI_H */
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@ -785,6 +785,7 @@ static int pci_setup_device(struct pci_dev * dev)
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static void pci_release_capabilities(struct pci_dev *dev)
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{
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pci_vpd_release(dev);
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pci_iov_release(dev);
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}
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/**
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@ -979,6 +980,9 @@ static void pci_init_capabilities(struct pci_dev *dev)
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/* Alternative Routing-ID Forwarding */
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pci_enable_ari(dev);
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/* Single Root I/O Virtualization */
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pci_iov_init(dev);
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}
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void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
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@ -93,6 +93,12 @@ enum {
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/* #6: expansion ROM resource */
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PCI_ROM_RESOURCE,
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/* device specific resources */
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#ifdef CONFIG_PCI_IOV
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PCI_IOV_RESOURCES,
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PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
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#endif
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/* resources assigned to buses behind the bridge */
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#define PCI_BRIDGE_RESOURCE_NUM 4
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@ -180,6 +186,7 @@ struct pci_cap_saved_state {
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struct pcie_link_state;
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struct pci_vpd;
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struct pci_sriov;
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/*
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* The pci_dev structure is used to describe PCI devices.
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@ -257,6 +264,7 @@ struct pci_dev {
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unsigned int is_managed:1;
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unsigned int is_pcie:1;
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unsigned int state_saved:1;
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unsigned int is_physfn:1;
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pci_dev_flags_t dev_flags;
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atomic_t enable_cnt; /* pci_enable_device has been called */
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@ -270,6 +278,9 @@ struct pci_dev {
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struct list_head msi_list;
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#endif
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struct pci_vpd *vpd;
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#ifdef CONFIG_PCI_IOV
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struct pci_sriov *sriov; /* SR-IOV capability related */
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#endif
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};
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extern struct pci_dev *alloc_pci_dev(void);
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@ -375,6 +375,7 @@
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#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
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#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
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#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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#define PCI_EXP_DEVCAP 4 /* Device capabilities */
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@ -498,6 +499,7 @@
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#define PCI_EXT_CAP_ID_DSN 3
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#define PCI_EXT_CAP_ID_PWR 4
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#define PCI_EXT_CAP_ID_ARI 14
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#define PCI_EXT_CAP_ID_SRIOV 16
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/* Advanced Error Reporting */
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#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
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@ -615,4 +617,35 @@
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#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
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#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
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/* Single Root I/O Virtualization */
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#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
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#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
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#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
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#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
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#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
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#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */
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#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */
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#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
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#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
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#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
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#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */
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#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
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#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
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#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
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#define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */
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#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
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#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
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#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
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#define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */
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#define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */
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#define PCI_SRIOV_BAR 0x24 /* VF BAR0 */
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#define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */
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#define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/
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#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */
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#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */
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#define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */
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#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */
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#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
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#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
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#endif /* LINUX_PCI_REGS_H */
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Loading…
Reference in New Issue