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clk: rockchip: fix rk3188 hsadc_frac definition

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The arguments to COMPOSITE_FRAC for hsadc_frac were mangled, leaving out the
the general clock flags argument. This results in strange effects, as only
sometimes a zero-division is reported as the wrong register is read.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Heiko Stübner 2014-10-30 14:26:13 +01:00 committed by Heiko Stuebner
parent 78eaf6095c
commit d1f931be7c
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3188.c
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@ -320,9 +320,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0, COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 6, GFLAGS), RK2928_CLKGATE_CON(2), 6, GFLAGS),
COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0,
RK2928_CLKSEL_CON(23), 0, RK2928_CLKSEL_CON(23), 0,
RK2928_CLKGATE_CON(2), 7, 0, GFLAGS), RK2928_CLKGATE_CON(2), 7, GFLAGS),
MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0, MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,
RK2928_CLKSEL_CON(22), 4, 2, MFLAGS), RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),