net/mlx4_core: Add basic elements for QCN
Add device capability, firmware command opcode and etc prior elements needed for QCN suppprt. Disable SRIOV VF view/access for QCN is disabled. While here, remove a redundant offset definition into the QUERY_DEV_CAP mailbox. Signed-off-by: Shani Michaeli <shanim@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
parent
c93682477b
commit
d237baa1cb
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@ -1499,6 +1499,15 @@ static struct mlx4_cmd_info cmd_info[] = {
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.verify = NULL,
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.verify = NULL,
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.wrapper = mlx4_ACCESS_REG_wrapper,
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.wrapper = mlx4_ACCESS_REG_wrapper,
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},
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},
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{
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.opcode = MLX4_CMD_CONGESTION_CTRL_OPCODE,
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.has_inbox = false,
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.has_outbox = false,
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.out_is_imm = false,
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.encode_slave_id = false,
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.verify = NULL,
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.wrapper = mlx4_CMD_EPERM_wrapper,
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},
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/* Native multicast commands are not available for guests */
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/* Native multicast commands are not available for guests */
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{
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{
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.opcode = MLX4_CMD_QP_ATTACH,
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.opcode = MLX4_CMD_QP_ATTACH,
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@ -143,7 +143,8 @@ static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
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[18] = "More than 80 VFs support",
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[18] = "More than 80 VFs support",
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[19] = "Performance optimized for limited rule configuration flow steering support",
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[19] = "Performance optimized for limited rule configuration flow steering support",
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[20] = "Recoverable error events support",
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[20] = "Recoverable error events support",
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[21] = "Port Remap support"
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[21] = "Port Remap support",
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[22] = "QCN support"
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};
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};
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int i;
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int i;
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@ -675,7 +676,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
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#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
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#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
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#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
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#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
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#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
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#define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a
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#define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b
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#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
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#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
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#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
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#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
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#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
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#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
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@ -777,6 +778,9 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
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dev_cap->fs_max_num_qp_per_entry = field;
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dev_cap->fs_max_num_qp_per_entry = field;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
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if (field & 0x1)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;
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MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
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MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
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dev_cap->stat_rate_support = stat_rate;
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dev_cap->stat_rate_support = stat_rate;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
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@ -1149,6 +1153,11 @@ int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
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DEV_CAP_EXT_2_FLAG_FSM);
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DEV_CAP_EXT_2_FLAG_FSM);
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MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
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MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
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/* turn off QCN for guests */
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MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
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field &= 0xfe;
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MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
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return 0;
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return 0;
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}
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}
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@ -163,6 +163,9 @@ enum {
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MLX4_QP_FLOW_STEERING_ATTACH = 0x65,
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MLX4_QP_FLOW_STEERING_ATTACH = 0x65,
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MLX4_QP_FLOW_STEERING_DETACH = 0x66,
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MLX4_QP_FLOW_STEERING_DETACH = 0x66,
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MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64,
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MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64,
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/* Update and read QCN parameters */
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MLX4_CMD_CONGESTION_CTRL_OPCODE = 0x68,
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};
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};
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enum {
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enum {
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@ -233,6 +236,16 @@ struct mlx4_config_dev_params {
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u8 rx_csum_flags_port_2;
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u8 rx_csum_flags_port_2;
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};
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};
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enum mlx4_en_congestion_control_algorithm {
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MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT = 0,
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};
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enum mlx4_en_congestion_control_opmod {
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MLX4_CONGESTION_CONTROL_GET_PARAMS,
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MLX4_CONGESTION_CONTROL_GET_STATISTICS,
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MLX4_CONGESTION_CONTROL_SET_PARAMS = 4,
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};
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struct mlx4_dev;
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struct mlx4_dev;
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struct mlx4_cmd_mailbox {
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struct mlx4_cmd_mailbox {
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@ -203,7 +203,8 @@ enum {
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MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
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MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
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MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
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MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
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MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
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MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
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MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21
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MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
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MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
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};
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};
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enum {
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enum {
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