[POWERPC] 4xx: Adds decoding of 440SPE memory size to boot wrapper library
This adds a function to the bootwrapper 4xx library to decode memory size on 440SPE processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>hifive-unleashed-5.1
Benjamin Herrenschmidt
Josh Boyer
parent
007b6aa811
commit
d23f509929
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@ -22,16 +22,14 @@
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#include "dcr.h"
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/* Read the 4xx SDRAM controller to get size of system memory. */
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void ibm4xx_fixup_memsize(void)
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void ibm4xx_sdram_fixup_memsize(void)
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{
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int i;
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unsigned long memsize, bank_config;
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memsize = 0;
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for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
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mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
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bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
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bank_config = SDRAM0_READ(sdram_bxcr[i]);
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if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
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memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
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}
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@ -39,6 +37,69 @@ void ibm4xx_fixup_memsize(void)
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dt_fixup_memory(0, memsize);
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}
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/* Read the 440SPe MQ controller to get size of system memory. */
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#define DCRN_MQ0_B0BAS 0x40
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#define DCRN_MQ0_B1BAS 0x41
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#define DCRN_MQ0_B2BAS 0x42
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#define DCRN_MQ0_B3BAS 0x43
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static u64 ibm440spe_decode_bas(u32 bas)
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{
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u64 base = ((u64)(bas & 0xFFE00000u)) << 2;
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/* open coded because I'm paranoid about invalid values */
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switch ((bas >> 4) & 0xFFF) {
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case 0:
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return 0;
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case 0xffc:
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return base + 0x000800000ull;
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case 0xff8:
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return base + 0x001000000ull;
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case 0xff0:
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return base + 0x002000000ull;
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case 0xfe0:
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return base + 0x004000000ull;
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case 0xfc0:
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return base + 0x008000000ull;
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case 0xf80:
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return base + 0x010000000ull;
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case 0xf00:
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return base + 0x020000000ull;
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case 0xe00:
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return base + 0x040000000ull;
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case 0xc00:
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return base + 0x080000000ull;
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case 0x800:
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return base + 0x100000000ull;
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}
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printf("Memory BAS value 0x%08x unsupported !\n", bas);
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return 0;
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}
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void ibm440spe_fixup_memsize(void)
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{
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u64 banktop, memsize = 0;
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/* Ultimately, we should directly construct the memory node
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* so we are able to handle holes in the memory address space
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*/
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS));
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if (banktop > memsize)
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memsize = banktop;
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS));
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if (banktop > memsize)
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memsize = banktop;
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS));
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if (banktop > memsize)
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memsize = banktop;
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS));
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if (banktop > memsize)
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memsize = banktop;
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dt_fixup_memory(0, memsize);
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}
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/* 4xx DDR1/2 Denali memory controller support */
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/* DDR0 registers */
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#define DDR0_02 2
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@ -77,19 +138,13 @@ void ibm4xx_fixup_memsize(void)
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#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
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static inline u32 mfdcr_sdram0(u32 reg)
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{
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mtdcr(DCRN_SDRAM0_CFGADDR, reg);
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return mfdcr(DCRN_SDRAM0_CFGDATA);
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}
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void ibm4xx_denali_fixup_memsize(void)
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{
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u32 val, max_cs, max_col, max_row;
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u32 cs, col, row, bank, dpath;
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unsigned long memsize;
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val = mfdcr_sdram0(DDR0_02);
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val = SDRAM0_READ(DDR0_02);
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if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
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fatal("DDR controller is not initialized\n");
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@ -99,7 +154,7 @@ void ibm4xx_denali_fixup_memsize(void)
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max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
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/* get CS value */
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val = mfdcr_sdram0(DDR0_10);
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val = SDRAM0_READ(DDR0_10);
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val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
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cs = 0;
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@ -115,7 +170,7 @@ void ibm4xx_denali_fixup_memsize(void)
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fatal("DDR wrong CS configuration\n");
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/* get data path bytes */
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val = mfdcr_sdram0(DDR0_14);
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val = SDRAM0_READ(DDR0_14);
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if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
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dpath = 8; /* 64 bits */
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@ -123,7 +178,7 @@ void ibm4xx_denali_fixup_memsize(void)
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dpath = 4; /* 32 bits */
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/* get address pins (rows) */
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val = mfdcr_sdram0(DDR0_42);
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val = SDRAM0_READ(DDR0_42);
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row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
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if (row > max_row)
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@ -131,7 +186,7 @@ void ibm4xx_denali_fixup_memsize(void)
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row = max_row - row;
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/* get collomn size and banks */
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val = mfdcr_sdram0(DDR0_43);
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val = SDRAM0_READ(DDR0_43);
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col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
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if (col > max_col)
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@ -11,7 +11,8 @@
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#ifndef _POWERPC_BOOT_4XX_H_
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#define _POWERPC_BOOT_4XX_H_
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void ibm4xx_fixup_memsize(void);
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void ibm4xx_sdram_fixup_memsize(void);
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void ibm440spe_fixup_memsize(void);
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void ibm4xx_denali_fixup_memsize(void);
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void ibm44x_dbcr_reset(void);
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void ibm40x_dbcr_reset(void);
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@ -31,7 +31,7 @@ static void bamboo_fixups(void)
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unsigned long sysclk = 33333333;
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ibm440ep_fixup_clocks(sysclk, 11059200);
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ibm4xx_fixup_memsize();
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ibm4xx_sdram_fixup_memsize();
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ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
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dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
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}
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@ -38,7 +38,7 @@ static void taishan_fixups(void)
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so we just use that code for now at least */
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ibm440ep_fixup_clocks(sysclk, 6 * 1843200);
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ibm4xx_fixup_memsize();
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ibm4xx_sdram_fixup_memsize();
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dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
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@ -14,12 +14,20 @@
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#define DCRN_SDRAM0_CFGADDR 0x010
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#define DCRN_SDRAM0_CFGDATA 0x011
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#define SDRAM0_READ(offset) ({\
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mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
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mfdcr(DCRN_SDRAM0_CFGDATA); })
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#define SDRAM0_WRITE(offset, data) ({\
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mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
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mtdcr(DCRN_SDRAM0_CFGDATA, data); })
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#define SDRAM0_B0CR 0x40
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#define SDRAM0_B1CR 0x44
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#define SDRAM0_B2CR 0x48
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#define SDRAM0_B3CR 0x4c
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static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR };
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static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
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SDRAM0_B2CR, SDRAM0_B3CR };
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#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
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#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
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@ -134,7 +134,7 @@ static void ebony_fixups(void)
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unsigned long sysclk = 33000000;
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ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
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ibm4xx_fixup_memsize();
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ibm4xx_sdram_fixup_memsize();
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dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
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ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
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ebony_flashsel_fixup();
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@ -63,7 +63,7 @@ static void walnut_flashsel_fixup(void)
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#define WALNUT_OPENBIOS_MAC_OFF 0xfffffe0b
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static void walnut_fixups(void)
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{
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ibm4xx_fixup_memsize();
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ibm4xx_sdram_fixup_memsize();
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ibm405gp_fixup_clocks(33330000, 0xa8c000);
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ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
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ibm4xx_fixup_ebc_ranges("/plb/ebc");
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