[SPARC64]: Initial sun4v TLB miss handling infrastructure.
Things are a little tricky because, unlike sun4u, we have to: 1) do a hypervisor trap to do the TLB load. 2) do the TSB lookup calculations by hand Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
840aaef8db
commit
d257d5da39
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@ -474,6 +474,7 @@ setup_tba:
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sparc64_boot_end:
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#include "systbls.S"
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#include "sun4v_tlb_miss.S"
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#include "ktlb.S"
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#include "tsb.S"
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#include "etrap.S"
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@ -16,12 +16,16 @@
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.text
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.align 32
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.globl kvmap_itlb
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kvmap_itlb:
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/* g6: TAG TARGET */
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_IMMU, %g4
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/* sun4v_itlb_miss branches here with the missing virtual
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* address already loaded into %g4
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*/
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kvmap_itlb_4v:
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kvmap_itlb_nonlinear:
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/* Catch kernel NULL pointer calls. */
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sethi %hi(PAGE_SIZE), %g5
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@ -94,11 +98,15 @@ kvmap_dtlb_obp:
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nop
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.align 32
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.globl kvmap_dtlb
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kvmap_dtlb:
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/* %g6: TAG TARGET */
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g4
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/* sun4v_dtlb_miss branches here with the missing virtual
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* address already loaded into %g4
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*/
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kvmap_dtlb_4v:
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brgez,pn %g4, kvmap_dtlb_nonlinear
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nop
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219
arch/sparc64/kernel/sun4v_tlb_miss.S
Normal file
219
arch/sparc64/kernel/sun4v_tlb_miss.S
Normal file
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@ -0,0 +1,219 @@
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/* sun4v_tlb_miss.S: Sun4v TLB miss handlers.
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*
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* Copyright (C) 2006 <davem@davemloft.net>
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*/
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.text
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.align 32
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sun4v_itlb_miss:
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/* Load CPU ID into %g3. */
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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/* Load UTSB reg into %g1. */
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ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1
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/* Load &trap_block[smp_processor_id()] into %g2. */
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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/* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6.
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* Branch if kernel TLB miss. The kernel TSB and user TSB miss
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* code wants the missing virtual address in %g4, so that value
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* cannot be modified through the entirety of this handler.
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*/
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
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srlx %g4, 22, %g3
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sllx %g5, 48, %g6
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or %g6, %g3, %g6
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brz,pn %g5, kvmap_itlb_4v
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nop
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/* Create TSB pointer. This is something like:
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*
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* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
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* tsb_base = tsb_reg & ~0x7UL;
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*/
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and %g1, 0x7, %g3
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andn %g1, 0x7, %g1
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mov 512, %g7
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sllx %g7, %g3, %g7
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sub %g7, 1, %g7
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/* TSB index mask is in %g7, tsb base is in %g1. Compute
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* the TSB entry pointer into %g1:
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*
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* tsb_index = ((vaddr >> PAGE_SHIFT) & tsb_mask);
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* tsb_ptr = tsb_base + (tsb_index * 16);
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*/
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srlx %g4, PAGE_SHIFT, %g3
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and %g3, %g7, %g3
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sllx %g3, 4, %g3
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add %g1, %g3, %g1
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/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
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ldda [%g1] ASI_QUAD_LDD_PHYS, %g2
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cmp %g2, %g6
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sethi %hi(_PAGE_EXEC), %g7
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bne,a,pn %xcc, tsb_miss_page_table_walk
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mov FAULT_CODE_ITLB, %g3
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andcc %g3, %g7, %g0
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be,a,pn %xcc, tsb_do_fault
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mov FAULT_CODE_ITLB, %g3
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/* We have a valid entry, make hypervisor call to load
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* I-TLB and return from trap.
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*
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* %g3: PTE
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* %g4: vaddr
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* %g6: TAG TARGET (only "CTX << 48" part matters)
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*/
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sun4v_itlb_load:
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mov %o0, %g1 ! save %o0
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mov %o1, %g2 ! save %o1
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mov %o2, %g5 ! save %o2
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mov %o3, %g7 ! save %o3
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mov %g4, %o0 ! vaddr
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srlx %g6, 48, %o1 ! ctx
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mov %g3, %o2 ! PTE
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mov HV_MMU_IMMU, %o3 ! flags
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ta HV_MMU_MAP_ADDR_TRAP
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mov %g1, %o0 ! restore %o0
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mov %g2, %o1 ! restore %o1
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mov %g5, %o2 ! restore %o2
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mov %g7, %o3 ! restore %o3
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retry
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sun4v_dtlb_miss:
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/* Load CPU ID into %g3. */
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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/* Load UTSB reg into %g1. */
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ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1
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/* Load &trap_block[smp_processor_id()] into %g2. */
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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/* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6.
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* Branch if kernel TLB miss. The kernel TSB and user TSB miss
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* code wants the missing virtual address in %g4, so that value
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* cannot be modified through the entirety of this handler.
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*/
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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srlx %g4, 22, %g3
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sllx %g5, 48, %g6
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or %g6, %g3, %g6
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brz,pn %g5, kvmap_dtlb_4v
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nop
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/* Create TSB pointer. This is something like:
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*
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* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
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* tsb_base = tsb_reg & ~0x7UL;
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*/
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and %g1, 0x7, %g3
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andn %g1, 0x7, %g1
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mov 512, %g7
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sllx %g7, %g3, %g7
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sub %g7, 1, %g7
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/* TSB index mask is in %g7, tsb base is in %g1. Compute
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* the TSB entry pointer into %g1:
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*
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* tsb_index = ((vaddr >> PAGE_SHIFT) & tsb_mask);
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* tsb_ptr = tsb_base + (tsb_index * 16);
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*/
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srlx %g4, PAGE_SHIFT, %g3
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and %g3, %g7, %g3
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sllx %g3, 4, %g3
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add %g1, %g3, %g1
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/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
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ldda [%g1] ASI_QUAD_LDD_PHYS, %g2
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cmp %g2, %g6
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bne,a,pn %xcc, tsb_miss_page_table_walk
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mov FAULT_CODE_ITLB, %g3
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/* We have a valid entry, make hypervisor call to load
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* D-TLB and return from trap.
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*
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* %g3: PTE
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* %g4: vaddr
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* %g6: TAG TARGET (only "CTX << 48" part matters)
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*/
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sun4v_dtlb_load:
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mov %o0, %g1 ! save %o0
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mov %o1, %g2 ! save %o1
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mov %o2, %g5 ! save %o2
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mov %o3, %g7 ! save %o3
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mov %g4, %o0 ! vaddr
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srlx %g6, 48, %o1 ! ctx
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mov %g3, %o2 ! PTE
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mov HV_MMU_DMMU, %o3 ! flags
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ta HV_MMU_MAP_ADDR_TRAP
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mov %g1, %o0 ! restore %o0
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mov %g2, %o1 ! restore %o1
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mov %g5, %o2 ! restore %o2
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mov %g7, %o3 ! restore %o3
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retry
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sun4v_dtlb_prot:
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/* Load CPU ID into %g3. */
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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/* Load &trap_block[smp_processor_id()] into %g2. */
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g5
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rdpr %tl, %g1
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cmp %g1, 1
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bgu,pn %xcc, winfix_trampoline
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nop
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ba,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
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#define BRANCH_ALWAYS 0x10680000
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#define NOP 0x01000000
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#define SUN4V_DO_PATCH(OLD, NEW) \
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sethi %hi(NEW), %g1; \
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or %g1, %lo(NEW), %g1; \
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sethi %hi(OLD), %g2; \
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or %g2, %lo(OLD), %g2; \
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sub %g1, %g2, %g1; \
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sethi %hi(BRANCH_ALWAYS), %g3; \
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srl %g1, 2, %g1; \
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or %g3, %lo(BRANCH_ALWAYS), %g3; \
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or %g3, %g1, %g3; \
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stw %g3, [%g2]; \
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sethi %hi(NOP), %g3; \
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or %g3, %lo(NOP), %g3; \
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stw %g3, [%g2 + 0x4]; \
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flush %g2;
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.globl sun4v_patch_tlb_handlers
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.type sun4v_patch_tlb_handlers,#function
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sun4v_patch_tlb_handlers:
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SUN4V_DO_PATCH(tl0_iamiss, sun4v_itlb_miss)
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SUN4V_DO_PATCH(tl1_iamiss, sun4v_itlb_miss)
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SUN4V_DO_PATCH(tl0_damiss, sun4v_dtlb_miss)
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SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss)
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SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot)
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SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot)
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retl
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nop
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.size sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers
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@ -18,30 +18,33 @@
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* %g4: available temporary
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* %g5: available temporary
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* %g6: TAG TARGET
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* %g7: physical address base of the linux page
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* %g7: available temporary, will be loaded by us with
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* the physical address base of the linux page
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* tables for the current address space
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*/
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.globl tsb_miss_dtlb
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tsb_miss_dtlb:
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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nop
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.globl tsb_miss_itlb
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tsb_miss_itlb:
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_IMMU, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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nop
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/* The sun4v TLB miss handlers jump directly here instead
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* of tsb_miss_{d,i}tlb with the missing virtual address
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* already loaded into %g4.
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*/
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tsb_miss_page_table_walk:
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TRAP_LOAD_PGD_PHYS(%g7, %g5)
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USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
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tsb_reload:
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TSB_LOCK_TAG(%g1, %g2, %g4)
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TSB_LOCK_TAG(%g1, %g2, %g7)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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* bother putting it into the TSB.
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*/
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srlx %g5, 32, %g2
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sethi %hi(_PAGE_ALL_SZ_BITS >> 32), %g4
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sethi %hi(_PAGE_ALL_SZ_BITS >> 32), %g7
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and %g2, %g7, %g2
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sethi %hi(_PAGE_SZBITS >> 32), %g7
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and %g2, %g4, %g2
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cmp %g2, %g7
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bne,a,pn %xcc, tsb_tlb_reload
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TSB_STORE(%g1, %g0)
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nop
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tsb_dtlb_load:
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stxa %g5, [%g0] ASI_DTLB_DATA_IN
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661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
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retry
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.section .gl_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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/* For sun4v the ASI_DTLB_DATA_IN store and the retry
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* instruction get nop'd out and we get here to branch
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* to the sun4v tlb load code. The registers are setup
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* as follows:
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*
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* %g4: vaddr
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* %g5: PTE
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* %g6: TAG
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*
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* The sun4v TLB load wants the PTE in %g3 so we fix that
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* up here.
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*/
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ba,pt %xcc, sun4v_dtlb_load
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mov %g5, %g3
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tsb_itlb_load:
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stxa %g5, [%g0] ASI_ITLB_DATA_IN
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661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
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retry
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.section .gl_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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/* For sun4v the ASI_ITLB_DATA_IN store and the retry
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* instruction get nop'd out and we get here to branch
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* to the sun4v tlb load code. The registers are setup
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* as follows:
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*
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* %g4: vaddr
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* %g5: PTE
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* %g6: TAG
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*
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* The sun4v TLB load wants the PTE in %g3 so we fix that
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* up here.
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*/
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ba,pt %xcc, sun4v_itlb_load
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mov %g5, %g3
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/* No valid entry in the page tables, do full fault
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* processing.
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nop
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tsb_do_dtlb_fault:
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rdpr %tl, %g4
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cmp %g4, 1
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mov TLB_TAG_ACCESS, %g4
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rdpr %tl, %g3
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cmp %g3, 1
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661: mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g5
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.section .gl_2insn_patch, "ax"
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.word 661b
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mov %g4, %g5
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nop
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.previous
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be,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_DTLB, %g4
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ba,pt %xcc, winfix_trampoline
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@ -196,12 +248,23 @@ __tsb_context_switch:
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add %g2, %g1, %g2
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stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
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mov TSB_REG, %g1
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661: mov TSB_REG, %g1
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stxa %o1, [%g1] ASI_DMMU
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.section .gl_2insn_patch, "ax"
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.word 661b
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mov SCRATCHPAD_UTSBREG1, %g1
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stxa %o1, [%g1] ASI_SCRATCHPAD
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.previous
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membar #Sync
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stxa %o1, [%g1] ASI_IMMU
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661: stxa %o1, [%g1] ASI_IMMU
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membar #Sync
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.section .gl_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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brz %o2, 9f
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nop
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@ -71,6 +71,9 @@ SECTIONS
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__con_initcall_end = .;
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SECURITY_INIT
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. = ALIGN(4);
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__tsb_ldquad_phys_patch = .;
|
||||
.tsb_ldquad_phys_patch : { *(.tsb_ldquad_phys_patch) }
|
||||
__tsb_ldquad_phys_patch_end = .;
|
||||
__tsb_phys_patch = .;
|
||||
.tsb_phys_patch : { *(.tsb_phys_patch) }
|
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__tsb_phys_patch_end = .;
|
||||
|
|
|
@ -1050,8 +1050,25 @@ unsigned long __init find_ecache_flush_span(unsigned long size)
|
|||
|
||||
static void __init tsb_phys_patch(void)
|
||||
{
|
||||
struct tsb_ldquad_phys_patch_entry *pquad;
|
||||
struct tsb_phys_patch_entry *p;
|
||||
|
||||
pquad = &__tsb_ldquad_phys_patch;
|
||||
while (pquad < &__tsb_ldquad_phys_patch_end) {
|
||||
unsigned long addr = pquad->addr;
|
||||
|
||||
if (tlb_type == hypervisor)
|
||||
*(unsigned int *) addr = pquad->sun4v_insn;
|
||||
else
|
||||
*(unsigned int *) addr = pquad->sun4u_insn;
|
||||
wmb();
|
||||
__asm__ __volatile__("flush %0"
|
||||
: /* no outputs */
|
||||
: "r" (addr));
|
||||
|
||||
pquad++;
|
||||
}
|
||||
|
||||
p = &__tsb_phys_patch;
|
||||
while (p < &__tsb_phys_patch_end) {
|
||||
unsigned long addr = p->addr;
|
||||
|
@ -1069,6 +1086,7 @@ static void __init tsb_phys_patch(void)
|
|||
/* paging_init() sets up the page tables */
|
||||
|
||||
extern void cheetah_ecache_flush_init(void);
|
||||
extern void sun4v_patch_tlb_handlers(void);
|
||||
|
||||
static unsigned long last_valid_pfn;
|
||||
pgd_t swapper_pg_dir[2048];
|
||||
|
@ -1078,9 +1096,13 @@ void __init paging_init(void)
|
|||
unsigned long end_pfn, pages_avail, shift;
|
||||
unsigned long real_end, i;
|
||||
|
||||
if (tlb_type == cheetah_plus)
|
||||
if (tlb_type == cheetah_plus ||
|
||||
tlb_type == hypervisor)
|
||||
tsb_phys_patch();
|
||||
|
||||
if (tlb_type == hypervisor)
|
||||
sun4v_patch_tlb_handlers();
|
||||
|
||||
/* Find available physical memory... */
|
||||
read_obp_memory("available", &pavail[0], &pavail_ents);
|
||||
|
||||
|
|
|
@ -6,6 +6,8 @@
|
|||
#ifndef _SPARC64_CPUDATA_H
|
||||
#define _SPARC64_CPUDATA_H
|
||||
|
||||
#include <asm/hypervisor.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/percpu.h>
|
||||
|
@ -57,6 +59,9 @@ struct trap_per_cpu {
|
|||
|
||||
/* D-cache line 2 */
|
||||
unsigned long __pad2[4];
|
||||
|
||||
/* Dcache lines 3 and 4 */
|
||||
struct hv_fault_status fault_info;
|
||||
} __attribute__((aligned(64)));
|
||||
extern struct trap_per_cpu trap_block[NR_CPUS];
|
||||
extern void init_cur_cpu_trap(void);
|
||||
|
@ -88,8 +93,9 @@ extern struct gl_2insn_patch_entry __gl_2insn_patch, __gl_2insn_patch_end;
|
|||
|
||||
#define TRAP_PER_CPU_THREAD 0x00
|
||||
#define TRAP_PER_CPU_PGD_PADDR 0x08
|
||||
#define TRAP_PER_CPU_FAULT_INFO 0x20
|
||||
|
||||
#define TRAP_BLOCK_SZ_SHIFT 6
|
||||
#define TRAP_BLOCK_SZ_SHIFT 7
|
||||
|
||||
#include <asm/scratchpad.h>
|
||||
|
||||
|
|
|
@ -53,6 +53,14 @@
|
|||
* kernel image, so we don't play these games for swapper_tsb access.
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
struct tsb_ldquad_phys_patch_entry {
|
||||
unsigned int addr;
|
||||
unsigned int sun4u_insn;
|
||||
unsigned int sun4v_insn;
|
||||
};
|
||||
extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
|
||||
__tsb_ldquad_phys_patch_end;
|
||||
|
||||
struct tsb_phys_patch_entry {
|
||||
unsigned int addr;
|
||||
unsigned int insn;
|
||||
|
@ -61,9 +69,10 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
|
|||
#endif
|
||||
#define TSB_LOAD_QUAD(TSB, REG) \
|
||||
661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
|
||||
.section .tsb_phys_patch, "ax"; \
|
||||
.section .tsb_ldquad_phys_patch, "ax"; \
|
||||
.word 661b; \
|
||||
ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
|
||||
ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
|
||||
.previous
|
||||
|
||||
#define TSB_LOAD_TAG_HIGH(TSB, REG) \
|
||||
|
|
Loading…
Reference in a new issue