ARM: imx6qdl: switch to use macro for clock ID
Instead of using enum for clock ID, let's switch imx6qdl clock driver to use macro. In this case, device tree can reuse these macros to improve readability. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>hifive-unleashed-5.1
Shawn Guo
parent
a25d67a437
commit
d2d2e54d66
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@ -7,223 +7,13 @@ Required properties:
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
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clocks and IDs.
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Clock ID
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---------------------------
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dummy 0
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ckil 1
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ckih 2
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osc 3
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pll2_pfd0_352m 4
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pll2_pfd1_594m 5
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pll2_pfd2_396m 6
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pll3_pfd0_720m 7
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pll3_pfd1_540m 8
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pll3_pfd2_508m 9
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pll3_pfd3_454m 10
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pll2_198m 11
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pll3_120m 12
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pll3_80m 13
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pll3_60m 14
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twd 15
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step 16
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pll1_sw 17
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periph_pre 18
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periph2_pre 19
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periph_clk2_sel 20
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periph2_clk2_sel 21
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axi_sel 22
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esai_sel 23
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asrc_sel 24
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spdif_sel 25
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gpu2d_axi 26
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gpu3d_axi 27
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gpu2d_core_sel 28
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gpu3d_core_sel 29
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gpu3d_shader_sel 30
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ipu1_sel 31
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ipu2_sel 32
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ldb_di0_sel 33
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ldb_di1_sel 34
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ipu1_di0_pre_sel 35
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ipu1_di1_pre_sel 36
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ipu2_di0_pre_sel 37
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ipu2_di1_pre_sel 38
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ipu1_di0_sel 39
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ipu1_di1_sel 40
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ipu2_di0_sel 41
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ipu2_di1_sel 42
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hsi_tx_sel 43
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pcie_axi_sel 44
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ssi1_sel 45
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ssi2_sel 46
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ssi3_sel 47
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usdhc1_sel 48
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usdhc2_sel 49
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usdhc3_sel 50
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usdhc4_sel 51
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enfc_sel 52
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emi_sel 53
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emi_slow_sel 54
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vdo_axi_sel 55
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vpu_axi_sel 56
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cko1_sel 57
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periph 58
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periph2 59
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periph_clk2 60
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periph2_clk2 61
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ipg 62
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ipg_per 63
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esai_pred 64
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esai_podf 65
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asrc_pred 66
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asrc_podf 67
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spdif_pred 68
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spdif_podf 69
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can_root 70
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ecspi_root 71
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gpu2d_core_podf 72
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gpu3d_core_podf 73
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gpu3d_shader 74
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ipu1_podf 75
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ipu2_podf 76
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ldb_di0_podf 77
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ldb_di1_podf 78
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ipu1_di0_pre 79
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ipu1_di1_pre 80
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ipu2_di0_pre 81
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ipu2_di1_pre 82
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hsi_tx_podf 83
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ssi1_pred 84
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ssi1_podf 85
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ssi2_pred 86
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ssi2_podf 87
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ssi3_pred 88
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ssi3_podf 89
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uart_serial_podf 90
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usdhc1_podf 91
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usdhc2_podf 92
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usdhc3_podf 93
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usdhc4_podf 94
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enfc_pred 95
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enfc_podf 96
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emi_podf 97
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emi_slow_podf 98
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vpu_axi_podf 99
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cko1_podf 100
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axi 101
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mmdc_ch0_axi_podf 102
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mmdc_ch1_axi_podf 103
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arm 104
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ahb 105
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apbh_dma 106
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asrc 107
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can1_ipg 108
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can1_serial 109
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can2_ipg 110
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can2_serial 111
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ecspi1 112
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ecspi2 113
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ecspi3 114
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ecspi4 115
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ecspi5 116
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enet 117
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esai 118
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gpt_ipg 119
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gpt_ipg_per 120
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gpu2d_core 121
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gpu3d_core 122
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hdmi_iahb 123
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hdmi_isfr 124
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i2c1 125
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i2c2 126
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i2c3 127
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iim 128
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enfc 129
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ipu1 130
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ipu1_di0 131
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ipu1_di1 132
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ipu2 133
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ipu2_di0 134
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ldb_di0 135
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ldb_di1 136
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ipu2_di1 137
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hsi_tx 138
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mlb 139
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mmdc_ch0_axi 140
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mmdc_ch1_axi 141
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ocram 142
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openvg_axi 143
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pcie_axi 144
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pwm1 145
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pwm2 146
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pwm3 147
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pwm4 148
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per1_bch 149
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gpmi_bch_apb 150
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gpmi_bch 151
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gpmi_io 152
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gpmi_apb 153
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sata 154
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sdma 155
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spba 156
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ssi1 157
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ssi2 158
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ssi3 159
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uart_ipg 160
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uart_serial 161
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usboh3 162
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usdhc1 163
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usdhc2 164
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usdhc3 165
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usdhc4 166
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vdo_axi 167
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vpu_axi 168
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cko1 169
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pll1_sys 170
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pll2_bus 171
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pll3_usb_otg 172
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pll4_audio 173
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pll5_video 174
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pll8_mlb 175
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pll7_usb_host 176
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pll6_enet 177
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ssi1_ipg 178
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ssi2_ipg 179
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ssi3_ipg 180
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rom 181
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usbphy1 182
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usbphy2 183
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ldb_di0_div_3_5 184
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ldb_di1_div_3_5 185
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sata_ref 186
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sata_ref_100m 187
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pcie_ref 188
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pcie_ref_125m 189
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enet_ref 190
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usbphy1_gate 191
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usbphy2_gate 192
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pll4_post_div 193
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pll5_post_div 194
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pll5_video_div 195
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eim_slow 196
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spdif 197
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cko2_sel 198
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cko2_podf 199
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cko2 200
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cko 201
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vdoa 202
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pll4_audio_div 203
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lvds1_sel 204
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lvds2_sel 205
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lvds1_gate 206
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lvds2_gate 207
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esai_ahb 208
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
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for the full list of i.MX6 Quad and DualLite clock IDs.
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Examples:
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#include <dt-bindings/clock/imx6qdl-clock.h>
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clks: ccm@020c4000 {
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compatible = "fsl,imx6q-ccm";
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reg = <0x020c4000 0x4000>;
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@ -235,7 +25,7 @@ uart1: serial@02020000 {
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compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
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reg = <0x02020000 0x4000>;
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interrupts = <0 26 0x04>;
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clocks = <&clks 160>, <&clks 161>;
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clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -19,6 +19,7 @@
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include "clk.h"
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#include "common.h"
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@ -73,48 +74,13 @@ static const char *lvds_sels[] = {
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"pcie_ref_125m", "sata_ref_100m",
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};
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enum mx6q_clks {
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dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
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pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
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pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
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periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
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esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
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gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
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ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
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ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
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ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
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usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
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emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
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periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
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asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
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gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
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ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
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ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
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ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
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usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
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emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
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mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
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can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
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esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
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hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
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ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
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mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
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gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
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ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
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usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
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pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
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ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
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sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
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usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
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spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
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lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max
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};
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static struct clk *clk[clk_max];
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static struct clk *clk[IMX6QDL_CLK_END];
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static struct clk_onecell_data clk_data;
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static enum mx6q_clks const clks_init_on[] __initconst = {
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mmdc_ch0_axi, rom, arm,
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static unsigned int const clks_init_on[] __initconst = {
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IMX6QDL_CLK_MMDC_CH0_AXI,
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IMX6QDL_CLK_ROM,
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IMX6QDL_CLK_ARM,
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};
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static struct clk_div_table clk_enet_ref_table[] = {
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@ -149,10 +115,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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int i;
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int ret;
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clk[dummy] = imx_clk_fixed("dummy", 0);
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clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
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clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
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clk[osc] = imx_obtain_fixed_clock("osc", 0);
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clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
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clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
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clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
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base = of_iomap(np, 0);
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@ -166,14 +132,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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video_div_table[2].div = 1;
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};
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/* type name parent_name base div_mask */
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clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
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clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
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clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
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clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
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clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
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clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
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clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
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/* type name parent_name base div_mask */
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clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
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clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
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clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
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clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
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clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
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clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
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clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
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/*
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* Bit 20 is the reserved and read-only bit, we do this only for:
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@ -181,28 +147,28 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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* - Keep refcount when do usbphy clk_enable/disable, in that case,
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* the clk framework may need to enable/disable usbphy's parent
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*/
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clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
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clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
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clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
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clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
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/*
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* usbphy*_gate needs to be on after system boots up, and software
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* never needs to control it anymore.
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*/
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clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
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clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
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clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
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clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
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clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
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clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
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clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
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clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
|
||||
|
||||
clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
|
||||
clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
|
||||
clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
|
||||
clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
|
||||
|
||||
clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
|
||||
clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
|
||||
base + 0xe0, 0, 2, 0, clk_enet_ref_table,
|
||||
&imx_ccm_lock);
|
||||
|
||||
clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
|
||||
/*
|
||||
* lvds1_gate and lvds2_gate are pseudo-gates. Both can be
|
||||
|
|
@ -210,29 +176,29 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
* the "output_enable" bit as a gate, even though it's really just
|
||||
* enabling clock output.
|
||||
*/
|
||||
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
|
||||
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
|
||||
clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
|
||||
clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
|
||||
|
||||
/* name parent_name reg idx */
|
||||
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
||||
clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
|
||||
clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
|
||||
clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
|
||||
clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
|
||||
clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
|
||||
clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
|
||||
/* name parent_name reg idx */
|
||||
clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
||||
clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
|
||||
clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
|
||||
|
||||
/* name parent_name mult div */
|
||||
clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
|
||||
clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
|
||||
clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
|
||||
/* name parent_name mult div */
|
||||
clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
|
||||
clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
|
||||
clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
|
||||
|
||||
clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
|
||||
clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
|
||||
|
||||
np = ccm_node;
|
||||
base = of_iomap(np, 0);
|
||||
|
|
@ -240,198 +206,197 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
imx6q_pm_set_ccm_base(base);
|
||||
|
||||
/* name reg shift width parent_names num_parents */
|
||||
clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
|
||||
clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
|
||||
clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
|
||||
clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
|
||||
clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
|
||||
clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
|
||||
clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
|
||||
clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
|
||||
clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
|
||||
clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
|
||||
clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
|
||||
clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
|
||||
clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
|
||||
clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
|
||||
clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
|
||||
clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
|
||||
clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
|
||||
clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
|
||||
/* name reg shift width parent_names num_parents */
|
||||
clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
|
||||
clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
|
||||
clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
|
||||
clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
|
||||
clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
|
||||
clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
|
||||
clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
|
||||
clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
|
||||
clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
|
||||
clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
|
||||
clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
|
||||
|
||||
/* name reg shift width busy: reg, shift parent_names num_parents */
|
||||
clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
|
||||
clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
|
||||
/* name reg shift width busy: reg, shift parent_names num_parents */
|
||||
clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
|
||||
|
||||
/* name parent_name reg shift width */
|
||||
clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
|
||||
clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
|
||||
clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
|
||||
clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
|
||||
clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
|
||||
clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
|
||||
clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
|
||||
clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
|
||||
clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
|
||||
clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
|
||||
clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
|
||||
clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
|
||||
clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
|
||||
clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
|
||||
clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
|
||||
clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
|
||||
clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
|
||||
clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
|
||||
clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
|
||||
clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
|
||||
clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
|
||||
clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
|
||||
clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
|
||||
clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
|
||||
clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
|
||||
clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
|
||||
clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
|
||||
clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
|
||||
clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
|
||||
clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
|
||||
clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
|
||||
clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
|
||||
clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
|
||||
clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
|
||||
clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
|
||||
clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
|
||||
clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
|
||||
clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
|
||||
clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
|
||||
clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
|
||||
/* name parent_name reg shift width */
|
||||
clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
|
||||
clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
|
||||
clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
|
||||
clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
|
||||
clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
|
||||
clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
|
||||
clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
|
||||
clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
|
||||
clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
|
||||
clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
|
||||
clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
|
||||
clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
|
||||
clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
|
||||
clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
|
||||
clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
|
||||
clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
|
||||
clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
|
||||
clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
|
||||
clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
|
||||
clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
|
||||
clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
|
||||
clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
|
||||
clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
|
||||
clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
|
||||
clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
|
||||
clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
|
||||
clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
|
||||
clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
|
||||
clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
|
||||
clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
|
||||
clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
|
||||
|
||||
/* name parent_name reg shift width busy: reg, shift */
|
||||
clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
|
||||
clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
|
||||
clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
|
||||
clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
|
||||
clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
|
||||
/* name parent_name reg shift width busy: reg, shift */
|
||||
clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
|
||||
clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
|
||||
clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
|
||||
clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
|
||||
clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
|
||||
|
||||
/* name parent_name reg shift */
|
||||
clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
|
||||
clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
|
||||
clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
|
||||
clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
|
||||
clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
|
||||
clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
|
||||
clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
|
||||
clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
|
||||
clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
|
||||
clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
|
||||
/* name parent_name reg shift */
|
||||
clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
|
||||
clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
|
||||
clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
|
||||
clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
|
||||
clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
|
||||
clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
|
||||
clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
|
||||
clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
|
||||
clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
|
||||
clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
|
||||
if (cpu_is_imx6dl())
|
||||
/* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
|
||||
clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
|
||||
clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
|
||||
else
|
||||
clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
|
||||
clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
|
||||
clk[esai] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
|
||||
clk[esai_ahb] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
|
||||
clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
|
||||
clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
|
||||
clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
|
||||
clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
|
||||
clk[IMX6QDL_CLK_ESAI] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
|
||||
clk[IMX6QDL_CLK_ESAI_AHB] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
|
||||
clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
|
||||
clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
|
||||
if (cpu_is_imx6dl())
|
||||
/*
|
||||
* The multiplexer and divider of imx6q clock gpu3d_shader get
|
||||
* redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
|
||||
*/
|
||||
clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
|
||||
else
|
||||
clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
|
||||
clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
|
||||
clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
|
||||
clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
|
||||
clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
|
||||
clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
|
||||
clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
|
||||
clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
|
||||
clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
|
||||
clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
|
||||
clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
|
||||
clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
|
||||
clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
|
||||
clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
|
||||
clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
|
||||
clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
|
||||
clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
|
||||
clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
|
||||
clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
|
||||
clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
|
||||
clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
|
||||
clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
|
||||
clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
|
||||
clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
|
||||
clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
|
||||
clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
|
||||
clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
|
||||
clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
|
||||
clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
|
||||
clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
|
||||
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
|
||||
clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
|
||||
if (cpu_is_imx6dl())
|
||||
/*
|
||||
* The multiplexer and divider of the imx6q clock gpu2d get
|
||||
* redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
|
||||
*/
|
||||
clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
|
||||
clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
|
||||
else
|
||||
clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
|
||||
clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
|
||||
clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
|
||||
clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
|
||||
clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
|
||||
clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
|
||||
clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
|
||||
clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
|
||||
clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
|
||||
clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
|
||||
clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
|
||||
clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
|
||||
clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
|
||||
clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
|
||||
clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
|
||||
clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
|
||||
clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
|
||||
clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
|
||||
clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
|
||||
clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
|
||||
clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
|
||||
clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
|
||||
clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
|
||||
clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
|
||||
clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
|
||||
clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
|
||||
clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
|
||||
clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
|
||||
clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
|
||||
clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
|
||||
clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
|
||||
clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
|
||||
clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
|
||||
clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
|
||||
clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
|
||||
clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
|
||||
clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
|
||||
clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
|
||||
clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
|
||||
clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
|
||||
clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
|
||||
clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
|
||||
clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
|
||||
clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
|
||||
clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
|
||||
clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
|
||||
clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
|
||||
clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
|
||||
clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
|
||||
clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
|
||||
clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
|
||||
clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
|
||||
clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
|
||||
clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
|
||||
clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
|
||||
clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
|
||||
clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
|
||||
clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
|
||||
clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
|
||||
clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
|
||||
clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
|
||||
clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
|
||||
clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
|
||||
clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
|
||||
clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
|
||||
clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
|
||||
clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
|
||||
clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
|
|
@ -439,54 +404,54 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
|
||||
clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
|
||||
|
||||
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
|
||||
cpu_is_imx6dl()) {
|
||||
clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
}
|
||||
|
||||
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
|
||||
clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
|
||||
clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
|
||||
clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
|
||||
|
||||
/*
|
||||
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
|
||||
* We can not get the 100MHz from the pll2_pfd0_352m.
|
||||
* So choose pll2_pfd2_396m as enfc_sel's parent.
|
||||
*/
|
||||
clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clk[clks_init_on[i]]);
|
||||
|
||||
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
|
||||
clk_prepare_enable(clk[usbphy1_gate]);
|
||||
clk_prepare_enable(clk[usbphy2_gate]);
|
||||
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
|
||||
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Let's initially set up CLKO with OSC24M, since this configuration
|
||||
* is widely used by imx6q board designs to clock audio codec.
|
||||
*/
|
||||
ret = clk_set_parent(clk[cko2_sel], clk[osc]);
|
||||
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
|
||||
if (!ret)
|
||||
ret = clk_set_parent(clk[cko], clk[cko2]);
|
||||
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
|
||||
if (ret)
|
||||
pr_warn("failed to set up CLKO: %d\n", ret);
|
||||
|
||||
/* Audio-related clocks configuration */
|
||||
clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
|
||||
|
||||
/* All existing boards with PCIe use LVDS1 */
|
||||
if (IS_ENABLED(CONFIG_PCI_IMX6))
|
||||
clk_set_parent(clk[lvds1_sel], clk[sata_ref_100m]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX6QDL_H
|
||||
|
||||
#define IMX6QDL_CLK_DUMMY 0
|
||||
#define IMX6QDL_CLK_CKIL 1
|
||||
#define IMX6QDL_CLK_CKIH 2
|
||||
#define IMX6QDL_CLK_OSC 3
|
||||
#define IMX6QDL_CLK_PLL2_PFD0_352M 4
|
||||
#define IMX6QDL_CLK_PLL2_PFD1_594M 5
|
||||
#define IMX6QDL_CLK_PLL2_PFD2_396M 6
|
||||
#define IMX6QDL_CLK_PLL3_PFD0_720M 7
|
||||
#define IMX6QDL_CLK_PLL3_PFD1_540M 8
|
||||
#define IMX6QDL_CLK_PLL3_PFD2_508M 9
|
||||
#define IMX6QDL_CLK_PLL3_PFD3_454M 10
|
||||
#define IMX6QDL_CLK_PLL2_198M 11
|
||||
#define IMX6QDL_CLK_PLL3_120M 12
|
||||
#define IMX6QDL_CLK_PLL3_80M 13
|
||||
#define IMX6QDL_CLK_PLL3_60M 14
|
||||
#define IMX6QDL_CLK_TWD 15
|
||||
#define IMX6QDL_CLK_STEP 16
|
||||
#define IMX6QDL_CLK_PLL1_SW 17
|
||||
#define IMX6QDL_CLK_PERIPH_PRE 18
|
||||
#define IMX6QDL_CLK_PERIPH2_PRE 19
|
||||
#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
|
||||
#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
|
||||
#define IMX6QDL_CLK_AXI_SEL 22
|
||||
#define IMX6QDL_CLK_ESAI_SEL 23
|
||||
#define IMX6QDL_CLK_ASRC_SEL 24
|
||||
#define IMX6QDL_CLK_SPDIF_SEL 25
|
||||
#define IMX6QDL_CLK_GPU2D_AXI 26
|
||||
#define IMX6QDL_CLK_GPU3D_AXI 27
|
||||
#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
|
||||
#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
|
||||
#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
|
||||
#define IMX6QDL_CLK_IPU1_SEL 31
|
||||
#define IMX6QDL_CLK_IPU2_SEL 32
|
||||
#define IMX6QDL_CLK_LDB_DI0_SEL 33
|
||||
#define IMX6QDL_CLK_LDB_DI1_SEL 34
|
||||
#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
|
||||
#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
|
||||
#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
|
||||
#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
|
||||
#define IMX6QDL_CLK_IPU1_DI0_SEL 39
|
||||
#define IMX6QDL_CLK_IPU1_DI1_SEL 40
|
||||
#define IMX6QDL_CLK_IPU2_DI0_SEL 41
|
||||
#define IMX6QDL_CLK_IPU2_DI1_SEL 42
|
||||
#define IMX6QDL_CLK_HSI_TX_SEL 43
|
||||
#define IMX6QDL_CLK_PCIE_AXI_SEL 44
|
||||
#define IMX6QDL_CLK_SSI1_SEL 45
|
||||
#define IMX6QDL_CLK_SSI2_SEL 46
|
||||
#define IMX6QDL_CLK_SSI3_SEL 47
|
||||
#define IMX6QDL_CLK_USDHC1_SEL 48
|
||||
#define IMX6QDL_CLK_USDHC2_SEL 49
|
||||
#define IMX6QDL_CLK_USDHC3_SEL 50
|
||||
#define IMX6QDL_CLK_USDHC4_SEL 51
|
||||
#define IMX6QDL_CLK_ENFC_SEL 52
|
||||
#define IMX6QDL_CLK_EMI_SEL 53
|
||||
#define IMX6QDL_CLK_EMI_SLOW_SEL 54
|
||||
#define IMX6QDL_CLK_VDO_AXI_SEL 55
|
||||
#define IMX6QDL_CLK_VPU_AXI_SEL 56
|
||||
#define IMX6QDL_CLK_CKO1_SEL 57
|
||||
#define IMX6QDL_CLK_PERIPH 58
|
||||
#define IMX6QDL_CLK_PERIPH2 59
|
||||
#define IMX6QDL_CLK_PERIPH_CLK2 60
|
||||
#define IMX6QDL_CLK_PERIPH2_CLK2 61
|
||||
#define IMX6QDL_CLK_IPG 62
|
||||
#define IMX6QDL_CLK_IPG_PER 63
|
||||
#define IMX6QDL_CLK_ESAI_PRED 64
|
||||
#define IMX6QDL_CLK_ESAI_PODF 65
|
||||
#define IMX6QDL_CLK_ASRC_PRED 66
|
||||
#define IMX6QDL_CLK_ASRC_PODF 67
|
||||
#define IMX6QDL_CLK_SPDIF_PRED 68
|
||||
#define IMX6QDL_CLK_SPDIF_PODF 69
|
||||
#define IMX6QDL_CLK_CAN_ROOT 70
|
||||
#define IMX6QDL_CLK_ECSPI_ROOT 71
|
||||
#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
|
||||
#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
|
||||
#define IMX6QDL_CLK_GPU3D_SHADER 74
|
||||
#define IMX6QDL_CLK_IPU1_PODF 75
|
||||
#define IMX6QDL_CLK_IPU2_PODF 76
|
||||
#define IMX6QDL_CLK_LDB_DI0_PODF 77
|
||||
#define IMX6QDL_CLK_LDB_DI1_PODF 78
|
||||
#define IMX6QDL_CLK_IPU1_DI0_PRE 79
|
||||
#define IMX6QDL_CLK_IPU1_DI1_PRE 80
|
||||
#define IMX6QDL_CLK_IPU2_DI0_PRE 81
|
||||
#define IMX6QDL_CLK_IPU2_DI1_PRE 82
|
||||
#define IMX6QDL_CLK_HSI_TX_PODF 83
|
||||
#define IMX6QDL_CLK_SSI1_PRED 84
|
||||
#define IMX6QDL_CLK_SSI1_PODF 85
|
||||
#define IMX6QDL_CLK_SSI2_PRED 86
|
||||
#define IMX6QDL_CLK_SSI2_PODF 87
|
||||
#define IMX6QDL_CLK_SSI3_PRED 88
|
||||
#define IMX6QDL_CLK_SSI3_PODF 89
|
||||
#define IMX6QDL_CLK_UART_SERIAL_PODF 90
|
||||
#define IMX6QDL_CLK_USDHC1_PODF 91
|
||||
#define IMX6QDL_CLK_USDHC2_PODF 92
|
||||
#define IMX6QDL_CLK_USDHC3_PODF 93
|
||||
#define IMX6QDL_CLK_USDHC4_PODF 94
|
||||
#define IMX6QDL_CLK_ENFC_PRED 95
|
||||
#define IMX6QDL_CLK_ENFC_PODF 96
|
||||
#define IMX6QDL_CLK_EMI_PODF 97
|
||||
#define IMX6QDL_CLK_EMI_SLOW_PODF 98
|
||||
#define IMX6QDL_CLK_VPU_AXI_PODF 99
|
||||
#define IMX6QDL_CLK_CKO1_PODF 100
|
||||
#define IMX6QDL_CLK_AXI 101
|
||||
#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
|
||||
#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
|
||||
#define IMX6QDL_CLK_ARM 104
|
||||
#define IMX6QDL_CLK_AHB 105
|
||||
#define IMX6QDL_CLK_APBH_DMA 106
|
||||
#define IMX6QDL_CLK_ASRC 107
|
||||
#define IMX6QDL_CLK_CAN1_IPG 108
|
||||
#define IMX6QDL_CLK_CAN1_SERIAL 109
|
||||
#define IMX6QDL_CLK_CAN2_IPG 110
|
||||
#define IMX6QDL_CLK_CAN2_SERIAL 111
|
||||
#define IMX6QDL_CLK_ECSPI1 112
|
||||
#define IMX6QDL_CLK_ECSPI2 113
|
||||
#define IMX6QDL_CLK_ECSPI3 114
|
||||
#define IMX6QDL_CLK_ECSPI4 115
|
||||
#define IMX6Q_CLK_ECSPI5 116
|
||||
#define IMX6DL_CLK_I2C4 116
|
||||
#define IMX6QDL_CLK_ENET 117
|
||||
#define IMX6QDL_CLK_ESAI 118
|
||||
#define IMX6QDL_CLK_GPT_IPG 119
|
||||
#define IMX6QDL_CLK_GPT_IPG_PER 120
|
||||
#define IMX6QDL_CLK_GPU2D_CORE 121
|
||||
#define IMX6QDL_CLK_GPU3D_CORE 122
|
||||
#define IMX6QDL_CLK_HDMI_IAHB 123
|
||||
#define IMX6QDL_CLK_HDMI_ISFR 124
|
||||
#define IMX6QDL_CLK_I2C1 125
|
||||
#define IMX6QDL_CLK_I2C2 126
|
||||
#define IMX6QDL_CLK_I2C3 127
|
||||
#define IMX6QDL_CLK_IIM 128
|
||||
#define IMX6QDL_CLK_ENFC 129
|
||||
#define IMX6QDL_CLK_IPU1 130
|
||||
#define IMX6QDL_CLK_IPU1_DI0 131
|
||||
#define IMX6QDL_CLK_IPU1_DI1 132
|
||||
#define IMX6QDL_CLK_IPU2 133
|
||||
#define IMX6QDL_CLK_IPU2_DI0 134
|
||||
#define IMX6QDL_CLK_LDB_DI0 135
|
||||
#define IMX6QDL_CLK_LDB_DI1 136
|
||||
#define IMX6QDL_CLK_IPU2_DI1 137
|
||||
#define IMX6QDL_CLK_HSI_TX 138
|
||||
#define IMX6QDL_CLK_MLB 139
|
||||
#define IMX6QDL_CLK_MMDC_CH0_AXI 140
|
||||
#define IMX6QDL_CLK_MMDC_CH1_AXI 141
|
||||
#define IMX6QDL_CLK_OCRAM 142
|
||||
#define IMX6QDL_CLK_OPENVG_AXI 143
|
||||
#define IMX6QDL_CLK_PCIE_AXI 144
|
||||
#define IMX6QDL_CLK_PWM1 145
|
||||
#define IMX6QDL_CLK_PWM2 146
|
||||
#define IMX6QDL_CLK_PWM3 147
|
||||
#define IMX6QDL_CLK_PWM4 148
|
||||
#define IMX6QDL_CLK_PER1_BCH 149
|
||||
#define IMX6QDL_CLK_GPMI_BCH_APB 150
|
||||
#define IMX6QDL_CLK_GPMI_BCH 151
|
||||
#define IMX6QDL_CLK_GPMI_IO 152
|
||||
#define IMX6QDL_CLK_GPMI_APB 153
|
||||
#define IMX6QDL_CLK_SATA 154
|
||||
#define IMX6QDL_CLK_SDMA 155
|
||||
#define IMX6QDL_CLK_SPBA 156
|
||||
#define IMX6QDL_CLK_SSI1 157
|
||||
#define IMX6QDL_CLK_SSI2 158
|
||||
#define IMX6QDL_CLK_SSI3 159
|
||||
#define IMX6QDL_CLK_UART_IPG 160
|
||||
#define IMX6QDL_CLK_UART_SERIAL 161
|
||||
#define IMX6QDL_CLK_USBOH3 162
|
||||
#define IMX6QDL_CLK_USDHC1 163
|
||||
#define IMX6QDL_CLK_USDHC2 164
|
||||
#define IMX6QDL_CLK_USDHC3 165
|
||||
#define IMX6QDL_CLK_USDHC4 166
|
||||
#define IMX6QDL_CLK_VDO_AXI 167
|
||||
#define IMX6QDL_CLK_VPU_AXI 168
|
||||
#define IMX6QDL_CLK_CKO1 169
|
||||
#define IMX6QDL_CLK_PLL1_SYS 170
|
||||
#define IMX6QDL_CLK_PLL2_BUS 171
|
||||
#define IMX6QDL_CLK_PLL3_USB_OTG 172
|
||||
#define IMX6QDL_CLK_PLL4_AUDIO 173
|
||||
#define IMX6QDL_CLK_PLL5_VIDEO 174
|
||||
#define IMX6QDL_CLK_PLL8_MLB 175
|
||||
#define IMX6QDL_CLK_PLL7_USB_HOST 176
|
||||
#define IMX6QDL_CLK_PLL6_ENET 177
|
||||
#define IMX6QDL_CLK_SSI1_IPG 178
|
||||
#define IMX6QDL_CLK_SSI2_IPG 179
|
||||
#define IMX6QDL_CLK_SSI3_IPG 180
|
||||
#define IMX6QDL_CLK_ROM 181
|
||||
#define IMX6QDL_CLK_USBPHY1 182
|
||||
#define IMX6QDL_CLK_USBPHY2 183
|
||||
#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
|
||||
#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
|
||||
#define IMX6QDL_CLK_SATA_REF 186
|
||||
#define IMX6QDL_CLK_SATA_REF_100M 187
|
||||
#define IMX6QDL_CLK_PCIE_REF 188
|
||||
#define IMX6QDL_CLK_PCIE_REF_125M 189
|
||||
#define IMX6QDL_CLK_ENET_REF 190
|
||||
#define IMX6QDL_CLK_USBPHY1_GATE 191
|
||||
#define IMX6QDL_CLK_USBPHY2_GATE 192
|
||||
#define IMX6QDL_CLK_PLL4_POST_DIV 193
|
||||
#define IMX6QDL_CLK_PLL5_POST_DIV 194
|
||||
#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
|
||||
#define IMX6QDL_CLK_EIM_SLOW 196
|
||||
#define IMX6QDL_CLK_SPDIF 197
|
||||
#define IMX6QDL_CLK_CKO2_SEL 198
|
||||
#define IMX6QDL_CLK_CKO2_PODF 199
|
||||
#define IMX6QDL_CLK_CKO2 200
|
||||
#define IMX6QDL_CLK_CKO 201
|
||||
#define IMX6QDL_CLK_VDOA 202
|
||||
#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
|
||||
#define IMX6QDL_CLK_LVDS1_SEL 204
|
||||
#define IMX6QDL_CLK_LVDS2_SEL 205
|
||||
#define IMX6QDL_CLK_LVDS1_GATE 206
|
||||
#define IMX6QDL_CLK_LVDS2_GATE 207
|
||||
#define IMX6QDL_CLK_ESAI_AHB 208
|
||||
#define IMX6QDL_CLK_END 209
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
|
||||
Loading…
Reference in New Issue