MMC core:
- Restore code to allow BKOPS and CACHE ctrl even if no HPI support - Reset HPI enabled state during re-init - Use a default minimum timeout when enabling CACHE ctrl MMC host: - omap_hsmmc: Fix DMA API warning - sdhci-tegra: Fix dt parsing of SDMMC pads autocal values - Correct register accesses when enabling v4 mode -----BEGIN PGP SIGNATURE----- iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAlwbZuAXHHVsZi5oYW5z c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjClwrQ//Qwfkk6goAozaNpvFawVLWy1y EHpjSfcipMiYrXaztRx7mrxslj/G0HNY7+272M6OSvv61zVb8s5cdTw6e23f98Td ZvswoOc5IWnfG1zfVPw2N+AvOMDlg1XNpS2IdjBt3M2WXf/vPBnG36wZlUFtt7TG exYXg55IArDwCBDVrP3NPEam+LjRglPKpetzSvh1NkuZRVBicLcry4kVpaOXU20V 2AbwSkGGTZenXnSez32hvP2k/Rj7WpcrkkgDKRmmKwu22mem+imhSlDBQFk5ZBFJ cr6NECYmsvPh7bWAlWzzi4nVSIVtmtlk7dIFRiAc1RHOjqtLBllZSCwsqdjQrV5a 8lugdk0gCSQhEkMwdcXDf6YzBznNrVFf7W5OZ0gzVYyEIfqkS1SMW585LkjSY6e4 iFRqWSB9kS9LWixPfyN2baxO7qSUGUFJA302d2DGvyRP2o7D9zWy3NOByfPtRbDl 7DKtiqSHy1LE/DF/meRiiy+wzvr1+uH2sYpfZ8/1gf0uEbdDb+96W8ghUDyVgisg u0UycCUXWBDpXyIT6QLdOIzO8kIsV2k9EJVe4sl7/rDrjGKCugRbUOav4cNFigvE hQrWd2BPYTqHz1rntAo34vMCrzPmkmlb78entgCTGLy4Tx7BIItVafuZoKS0jqcL h9bbH4C17eNYcQFB3nQ= =zypg -----END PGP SIGNATURE----- Merge tag 'mmc-v4.20-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC fixes from Ulf Hansson: "MMC core: - Restore code to allow BKOPS and CACHE ctrl even if no HPI support - Reset HPI enabled state during re-init - Use a default minimum timeout when enabling CACHE ctrl MMC host: - omap_hsmmc: Fix DMA API warning - sdhci-tegra: Fix dt parsing of SDMMC pads autocal values - Correct register accesses when enabling v4 mode" * tag 'mmc-v4.20-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: core: Use a minimum 1600ms timeout when enabling CACHE ctrl mmc: core: Allow BKOPS and CACHE ctrl even if no HPI support mmc: core: Reset HPI enabled state during re-init and in case of errors mmc: omap_hsmmc: fix DMA API warning mmc: tegra: Fix for SDMMC pads autocal parsing from dt mmc: sdhci: Fix sdhci_do_enable_v4_mode
This commit is contained in:
commit
d31aeb78c6
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@ -30,6 +30,7 @@
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#include "pwrseq.h"
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#include "pwrseq.h"
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#define DEFAULT_CMD6_TIMEOUT_MS 500
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#define DEFAULT_CMD6_TIMEOUT_MS 500
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#define MIN_CACHE_EN_TIMEOUT_MS 1600
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static const unsigned int tran_exp[] = {
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static const unsigned int tran_exp[] = {
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10000, 100000, 1000000, 10000000,
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10000, 100000, 1000000, 10000000,
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@ -526,8 +527,7 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
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card->cid.year += 16;
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card->cid.year += 16;
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/* check whether the eMMC card supports BKOPS */
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/* check whether the eMMC card supports BKOPS */
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if (!mmc_card_broken_hpi(card) &&
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if (ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1) {
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ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1) {
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card->ext_csd.bkops = 1;
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card->ext_csd.bkops = 1;
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card->ext_csd.man_bkops_en =
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card->ext_csd.man_bkops_en =
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(ext_csd[EXT_CSD_BKOPS_EN] &
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(ext_csd[EXT_CSD_BKOPS_EN] &
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@ -1782,20 +1782,26 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
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if (err) {
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if (err) {
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pr_warn("%s: Enabling HPI failed\n",
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pr_warn("%s: Enabling HPI failed\n",
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mmc_hostname(card->host));
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mmc_hostname(card->host));
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card->ext_csd.hpi_en = 0;
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err = 0;
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err = 0;
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} else
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} else {
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card->ext_csd.hpi_en = 1;
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card->ext_csd.hpi_en = 1;
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}
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}
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}
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/*
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/*
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* If cache size is higher than 0, this indicates
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* If cache size is higher than 0, this indicates the existence of cache
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* the existence of cache and it can be turned on.
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* and it can be turned on. Note that some eMMCs from Micron has been
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* reported to need ~800 ms timeout, while enabling the cache after
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* sudden power failure tests. Let's extend the timeout to a minimum of
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* DEFAULT_CACHE_EN_TIMEOUT_MS and do it for all cards.
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*/
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*/
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if (!mmc_card_broken_hpi(card) &&
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if (card->ext_csd.cache_size > 0) {
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card->ext_csd.cache_size > 0) {
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unsigned int timeout_ms = MIN_CACHE_EN_TIMEOUT_MS;
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timeout_ms = max(card->ext_csd.generic_cmd6_time, timeout_ms);
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err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
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err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
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EXT_CSD_CACHE_CTRL, 1,
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EXT_CSD_CACHE_CTRL, 1, timeout_ms);
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card->ext_csd.generic_cmd6_time);
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if (err && err != -EBADMSG)
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if (err && err != -EBADMSG)
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goto free_card;
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goto free_card;
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@ -1909,7 +1909,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
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mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
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mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
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mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
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mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
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mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
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mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
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mmc->max_seg_size = mmc->max_req_size;
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mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
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mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
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MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23;
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MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23;
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@ -1939,6 +1938,17 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
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goto err_irq;
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goto err_irq;
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}
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}
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/*
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* Limit the maximum segment size to the lower of the request size
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* and the DMA engine device segment size limits. In reality, with
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* 32-bit transfers, the DMA engine can do longer segments than this
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* but there is no way to represent that in the DMA model - if we
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* increase this figure here, we get warnings from the DMA API debug.
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*/
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mmc->max_seg_size = min3(mmc->max_req_size,
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dma_get_max_seg_size(host->rx_chan->device->dev),
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dma_get_max_seg_size(host->tx_chan->device->dev));
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/* Request IRQ for MMC operations */
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/* Request IRQ for MMC operations */
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ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
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ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
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mmc_hostname(mmc), host);
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mmc_hostname(mmc), host);
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@ -510,25 +510,25 @@ static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
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err = device_property_read_u32(host->mmc->parent,
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-3v3-timeout",
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"nvidia,pad-autocal-pull-up-offset-3v3-timeout",
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&autocal->pull_up_3v3);
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&autocal->pull_up_3v3_timeout);
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if (err)
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if (err)
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autocal->pull_up_3v3_timeout = 0;
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autocal->pull_up_3v3_timeout = 0;
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err = device_property_read_u32(host->mmc->parent,
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-3v3-timeout",
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"nvidia,pad-autocal-pull-down-offset-3v3-timeout",
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&autocal->pull_down_3v3);
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&autocal->pull_down_3v3_timeout);
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if (err)
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if (err)
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autocal->pull_down_3v3_timeout = 0;
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autocal->pull_down_3v3_timeout = 0;
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err = device_property_read_u32(host->mmc->parent,
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-1v8-timeout",
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"nvidia,pad-autocal-pull-up-offset-1v8-timeout",
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&autocal->pull_up_1v8);
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&autocal->pull_up_1v8_timeout);
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if (err)
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if (err)
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autocal->pull_up_1v8_timeout = 0;
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autocal->pull_up_1v8_timeout = 0;
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err = device_property_read_u32(host->mmc->parent,
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-1v8-timeout",
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"nvidia,pad-autocal-pull-down-offset-1v8-timeout",
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&autocal->pull_down_1v8);
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&autocal->pull_down_1v8_timeout);
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if (err)
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if (err)
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autocal->pull_down_1v8_timeout = 0;
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autocal->pull_down_1v8_timeout = 0;
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{
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{
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u16 ctrl2;
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u16 ctrl2;
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ctrl2 = sdhci_readb(host, SDHCI_HOST_CONTROL2);
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ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (ctrl2 & SDHCI_CTRL_V4_MODE)
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if (ctrl2 & SDHCI_CTRL_V4_MODE)
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return;
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return;
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ctrl2 |= SDHCI_CTRL_V4_MODE;
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ctrl2 |= SDHCI_CTRL_V4_MODE;
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sdhci_writeb(host, ctrl2, SDHCI_HOST_CONTROL);
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sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
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}
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}
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/*
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/*
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