drm/i915/bdw: Cleanup pre prod workarounds
as these have been fixed in production hw and hurt performance if applied. v2: adjust requested ring space (Ville) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482 Tested-by: zhoujian <jianx.zhou@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
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* update the number of dwords required based on the
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* actual number of workarounds applied
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*/
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ret = intel_ring_begin(ring, 24);
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ret = intel_ring_begin(ring, 18);
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if (ret)
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return ret;
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@ -722,19 +722,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
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intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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/*
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* This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
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* pre-production hardware
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*/
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intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
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_MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
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| GEN8_SAMPLER_POWER_BYPASS_DIS));
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intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1,
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_MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
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intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2,
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_MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
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_MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
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/* Use Force Non-Coherent whenever executing a 3D context. This is a
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* workaround for for a possible hang in the unlikely event a TLB
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