drm/armada: move primary plane to separate file
Split out the primary plane support; this is now entirely separate from the CRTC support. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>hifive-unleashed-5.1
Russell King
parent
3acea7b9b6
commit
d40af7b1ae
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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armada-y := armada_crtc.o armada_drv.o armada_fb.o armada_fbdev.o \
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armada_gem.o armada_overlay.o armada_trace.o
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armada_gem.o armada_overlay.o armada_plane.o armada_trace.o
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armada-y += armada_510.o
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armada-$(CONFIG_DEBUG_FS) += armada_debugfs.o
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@ -20,6 +20,7 @@
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#include "armada_fb.h"
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#include "armada_gem.h"
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#include "armada_hw.h"
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#include "armada_plane.h"
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#include "armada_trace.h"
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enum csc_mode {
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@ -30,23 +31,6 @@ enum csc_mode {
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CSC_RGB_STUDIO = 2,
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};
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static const uint32_t armada_primary_formats[] = {
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DRM_FORMAT_UYVY,
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DRM_FORMAT_YUYV,
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DRM_FORMAT_VYUY,
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DRM_FORMAT_YVYU,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_ABGR1555,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_BGR565,
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};
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/*
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* A note about interlacing. Let's consider HDMI 1920x1080i.
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* The timing parameters we have from X are:
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@ -160,57 +144,6 @@ static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
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}
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}
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void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
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int x, int y)
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{
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const struct drm_format_info *format = fb->format;
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unsigned int num_planes = format->num_planes;
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u32 addr = drm_fb_obj(fb)->dev_addr;
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int i;
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if (num_planes > 3)
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num_planes = 3;
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addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
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x * format->cpp[0];
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y /= format->vsub;
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x /= format->hsub;
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for (i = 1; i < num_planes; i++)
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addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
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x * format->cpp[i];
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for (; i < 3; i++)
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addrs[i] = 0;
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}
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static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
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int x, int y, struct armada_regs *regs, bool interlaced)
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{
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unsigned pitch = fb->pitches[0];
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u32 addrs[3], addr_odd, addr_even;
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unsigned i = 0;
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DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
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pitch, x, y, fb->format->cpp[0] * 8);
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armada_drm_plane_calc_addrs(addrs, fb, x, y);
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addr_odd = addr_even = addrs[0];
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if (interlaced) {
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addr_even += pitch;
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pitch *= 2;
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}
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/* write offset, base, and pitch */
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armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
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armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
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armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
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return i;
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}
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static void armada_drm_plane_work_call(struct armada_crtc *dcrtc,
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struct armada_plane_work *work,
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void (*fn)(struct armada_crtc *, struct armada_plane_work *))
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@ -1067,194 +1000,6 @@ static const struct drm_crtc_funcs armada_crtc_funcs = {
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.disable_vblank = armada_drm_crtc_disable_vblank,
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};
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int armada_drm_plane_prepare_fb(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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DRM_DEBUG_KMS("[PLANE:%d:%s] [FB:%d]\n",
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plane->base.id, plane->name,
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state->fb ? state->fb->base.id : 0);
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/*
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* Take a reference on the new framebuffer - we want to
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* hold on to it while the hardware is displaying it.
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*/
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if (state->fb)
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drm_framebuffer_get(state->fb);
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return 0;
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}
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void armada_drm_plane_cleanup_fb(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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DRM_DEBUG_KMS("[PLANE:%d:%s] [FB:%d]\n",
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plane->base.id, plane->name,
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old_state->fb ? old_state->fb->base.id : 0);
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if (old_state->fb)
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drm_framebuffer_put(old_state->fb);
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}
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int armada_drm_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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if (state->fb && !WARN_ON(!state->crtc)) {
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struct drm_crtc *crtc = state->crtc;
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struct drm_crtc_state *crtc_state;
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if (state->state)
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crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
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else
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crtc_state = crtc->state;
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return drm_atomic_helper_check_plane_state(state, crtc_state,
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0, INT_MAX,
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true, false);
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} else {
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state->visible = false;
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}
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return 0;
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}
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static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct drm_plane_state *state = plane->state;
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struct armada_crtc *dcrtc;
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struct armada_regs *regs;
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u32 cfg, cfg_mask, val;
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unsigned int idx;
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DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
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if (!state->fb || WARN_ON(!state->crtc))
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return;
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DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
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plane->base.id, plane->name,
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state->crtc->base.id, state->crtc->name,
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state->fb->base.id,
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old_state->visible, state->visible);
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dcrtc = drm_to_armada_crtc(state->crtc);
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regs = dcrtc->regs + dcrtc->regs_idx;
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idx = 0;
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if (!old_state->visible && state->visible) {
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val = CFG_PDWN64x66;
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if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420)
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val |= CFG_PDWN256x24;
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armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);
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}
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val = armada_rect_hw_fp(&state->src);
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if (armada_rect_hw_fp(&old_state->src) != val)
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armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);
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val = armada_rect_yx(&state->dst);
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if (armada_rect_yx(&old_state->dst) != val)
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armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);
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val = armada_rect_hw(&state->dst);
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if (armada_rect_hw(&old_state->dst) != val)
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armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);
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if (old_state->src.x1 != state->src.x1 ||
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old_state->src.y1 != state->src.y1 ||
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old_state->fb != state->fb) {
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idx += armada_drm_crtc_calc_fb(state->fb,
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state->src.x1 >> 16,
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state->src.y1 >> 16,
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regs + idx,
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dcrtc->interlaced);
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}
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if (old_state->fb != state->fb) {
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cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |
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CFG_GRA_MOD(drm_fb_to_armada_fb(state->fb)->mod);
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if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420)
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cfg |= CFG_PALETTE_ENA;
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if (state->visible)
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cfg |= CFG_GRA_ENA;
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if (dcrtc->interlaced)
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cfg |= CFG_GRA_FTOGGLE;
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cfg_mask = CFG_GRAFORMAT |
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CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
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CFG_SWAPYU | CFG_YUV2RGB) |
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CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
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CFG_GRA_ENA;
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} else if (old_state->visible != state->visible) {
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cfg = state->visible ? CFG_GRA_ENA : 0;
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cfg_mask = CFG_GRA_ENA;
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} else {
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cfg = cfg_mask = 0;
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}
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if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) ||
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drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) {
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cfg_mask |= CFG_GRA_HSMOOTH;
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if (drm_rect_width(&state->src) >> 16 !=
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drm_rect_width(&state->dst))
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cfg |= CFG_GRA_HSMOOTH;
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}
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if (cfg_mask)
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armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
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LCD_SPU_DMA_CTRL0);
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dcrtc->regs_idx += idx;
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}
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static void armada_drm_primary_plane_atomic_disable(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct armada_crtc *dcrtc;
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struct armada_regs *regs;
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unsigned int idx = 0;
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DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
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if (!old_state->crtc)
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return;
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DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n",
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plane->base.id, plane->name,
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old_state->crtc->base.id, old_state->crtc->name,
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old_state->fb->base.id);
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dcrtc = drm_to_armada_crtc(old_state->crtc);
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regs = dcrtc->regs + dcrtc->regs_idx;
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/* Disable plane and power down most RAMs and FIFOs */
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armada_reg_queue_mod(regs, idx, 0, CFG_GRA_ENA, LCD_SPU_DMA_CTRL0);
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armada_reg_queue_mod(regs, idx, CFG_PDWN256x32 | CFG_PDWN256x24 |
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CFG_PDWN256x8 | CFG_PDWN32x32 | CFG_PDWN64x66,
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0, LCD_SPU_SRAM_PARA1);
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dcrtc->regs_idx += idx;
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}
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static const struct drm_plane_helper_funcs armada_primary_plane_helper_funcs = {
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.prepare_fb = armada_drm_plane_prepare_fb,
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.cleanup_fb = armada_drm_plane_cleanup_fb,
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.atomic_check = armada_drm_plane_atomic_check,
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.atomic_update = armada_drm_primary_plane_atomic_update,
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.atomic_disable = armada_drm_primary_plane_atomic_disable,
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};
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static const struct drm_plane_funcs armada_primary_plane_funcs = {
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.update_plane = drm_plane_helper_update,
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.disable_plane = drm_plane_helper_disable,
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.destroy = drm_primary_helper_destroy,
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.reset = drm_atomic_helper_plane_reset,
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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};
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int armada_drm_plane_init(struct armada_plane *plane)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(plane->works); i++)
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plane->works[i].plane = &plane->base;
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init_waitqueue_head(&plane->frame_wait);
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return 0;
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}
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static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
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{ CSC_AUTO, "Auto" },
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{ CSC_YUV_CCIR601, "CCIR601" },
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@ -1363,21 +1108,7 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
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goto err_crtc;
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}
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ret = armada_drm_plane_init(primary);
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if (ret) {
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kfree(primary);
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goto err_crtc;
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}
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drm_plane_helper_add(&primary->base,
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&armada_primary_plane_helper_funcs);
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ret = drm_universal_plane_init(drm, &primary->base, 0,
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&armada_primary_plane_funcs,
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armada_primary_formats,
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ARRAY_SIZE(armada_primary_formats),
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NULL,
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DRM_PLANE_TYPE_PRIMARY, NULL);
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ret = armada_drm_primary_plane_init(drm, primary);
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if (ret) {
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kfree(primary);
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goto err_crtc;
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@ -54,21 +54,11 @@ struct armada_plane {
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};
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#define drm_to_armada_plane(p) container_of(p, struct armada_plane, base)
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int armada_drm_plane_init(struct armada_plane *plane);
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int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
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struct armada_plane_work *work);
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int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout);
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void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc,
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struct armada_plane *plane);
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void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
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int x, int y);
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int armada_drm_plane_prepare_fb(struct drm_plane *plane,
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struct drm_plane_state *state);
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void armada_drm_plane_cleanup_fb(struct drm_plane *plane,
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struct drm_plane_state *old_state);
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int armada_drm_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state);
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struct armada_crtc {
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struct drm_crtc crtc;
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@ -10,13 +10,14 @@
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/armada_drm.h>
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#include "armada_crtc.h"
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#include "armada_drm.h"
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#include "armada_fb.h"
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#include "armada_gem.h"
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#include "armada_hw.h"
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#include <drm/armada_drm.h>
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#include "armada_ioctlP.h"
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#include "armada_plane.h"
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#include "armada_trace.h"
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struct armada_ovl_plane_properties {
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@ -0,0 +1,297 @@
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/*
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* Copyright (C) 2012 Russell King
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* Rewritten from the dovefb driver, and Armada510 manuals.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "armada_crtc.h"
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#include "armada_drm.h"
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#include "armada_fb.h"
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#include "armada_gem.h"
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#include "armada_hw.h"
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#include "armada_plane.h"
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#include "armada_trace.h"
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static const uint32_t armada_primary_formats[] = {
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DRM_FORMAT_UYVY,
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DRM_FORMAT_YUYV,
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DRM_FORMAT_VYUY,
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DRM_FORMAT_YVYU,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_ABGR1555,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_BGR565,
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};
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void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
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int x, int y)
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{
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const struct drm_format_info *format = fb->format;
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unsigned int num_planes = format->num_planes;
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u32 addr = drm_fb_obj(fb)->dev_addr;
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int i;
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if (num_planes > 3)
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num_planes = 3;
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addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
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x * format->cpp[0];
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y /= format->vsub;
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x /= format->hsub;
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for (i = 1; i < num_planes; i++)
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addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
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x * format->cpp[i];
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for (; i < 3; i++)
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addrs[i] = 0;
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}
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static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
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int x, int y, struct armada_regs *regs, bool interlaced)
|
||||
{
|
||||
unsigned pitch = fb->pitches[0];
|
||||
u32 addrs[3], addr_odd, addr_even;
|
||||
unsigned i = 0;
|
||||
|
||||
DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
|
||||
pitch, x, y, fb->format->cpp[0] * 8);
|
||||
|
||||
armada_drm_plane_calc_addrs(addrs, fb, x, y);
|
||||
|
||||
addr_odd = addr_even = addrs[0];
|
||||
|
||||
if (interlaced) {
|
||||
addr_even += pitch;
|
||||
pitch *= 2;
|
||||
}
|
||||
|
||||
/* write offset, base, and pitch */
|
||||
armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
|
||||
armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
|
||||
armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
int armada_drm_plane_prepare_fb(struct drm_plane *plane,
|
||||
struct drm_plane_state *state)
|
||||
{
|
||||
DRM_DEBUG_KMS("[PLANE:%d:%s] [FB:%d]\n",
|
||||
plane->base.id, plane->name,
|
||||
state->fb ? state->fb->base.id : 0);
|
||||
|
||||
/*
|
||||
* Take a reference on the new framebuffer - we want to
|
||||
* hold on to it while the hardware is displaying it.
|
||||
*/
|
||||
if (state->fb)
|
||||
drm_framebuffer_get(state->fb);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void armada_drm_plane_cleanup_fb(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state)
|
||||
{
|
||||
DRM_DEBUG_KMS("[PLANE:%d:%s] [FB:%d]\n",
|
||||
plane->base.id, plane->name,
|
||||
old_state->fb ? old_state->fb->base.id : 0);
|
||||
|
||||
if (old_state->fb)
|
||||
drm_framebuffer_put(old_state->fb);
|
||||
}
|
||||
|
||||
int armada_drm_plane_atomic_check(struct drm_plane *plane,
|
||||
struct drm_plane_state *state)
|
||||
{
|
||||
if (state->fb && !WARN_ON(!state->crtc)) {
|
||||
struct drm_crtc *crtc = state->crtc;
|
||||
struct drm_crtc_state *crtc_state;
|
||||
|
||||
if (state->state)
|
||||
crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
|
||||
else
|
||||
crtc_state = crtc->state;
|
||||
return drm_atomic_helper_check_plane_state(state, crtc_state,
|
||||
0, INT_MAX,
|
||||
true, false);
|
||||
} else {
|
||||
state->visible = false;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state)
|
||||
{
|
||||
struct drm_plane_state *state = plane->state;
|
||||
struct armada_crtc *dcrtc;
|
||||
struct armada_regs *regs;
|
||||
u32 cfg, cfg_mask, val;
|
||||
unsigned int idx;
|
||||
|
||||
DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
|
||||
|
||||
if (!state->fb || WARN_ON(!state->crtc))
|
||||
return;
|
||||
|
||||
DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
|
||||
plane->base.id, plane->name,
|
||||
state->crtc->base.id, state->crtc->name,
|
||||
state->fb->base.id,
|
||||
old_state->visible, state->visible);
|
||||
|
||||
dcrtc = drm_to_armada_crtc(state->crtc);
|
||||
regs = dcrtc->regs + dcrtc->regs_idx;
|
||||
|
||||
idx = 0;
|
||||
if (!old_state->visible && state->visible) {
|
||||
val = CFG_PDWN64x66;
|
||||
if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420)
|
||||
val |= CFG_PDWN256x24;
|
||||
armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);
|
||||
}
|
||||
val = armada_rect_hw_fp(&state->src);
|
||||
if (armada_rect_hw_fp(&old_state->src) != val)
|
||||
armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);
|
||||
val = armada_rect_yx(&state->dst);
|
||||
if (armada_rect_yx(&old_state->dst) != val)
|
||||
armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);
|
||||
val = armada_rect_hw(&state->dst);
|
||||
if (armada_rect_hw(&old_state->dst) != val)
|
||||
armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);
|
||||
if (old_state->src.x1 != state->src.x1 ||
|
||||
old_state->src.y1 != state->src.y1 ||
|
||||
old_state->fb != state->fb) {
|
||||
idx += armada_drm_crtc_calc_fb(state->fb,
|
||||
state->src.x1 >> 16,
|
||||
state->src.y1 >> 16,
|
||||
regs + idx,
|
||||
dcrtc->interlaced);
|
||||
}
|
||||
if (old_state->fb != state->fb) {
|
||||
cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |
|
||||
CFG_GRA_MOD(drm_fb_to_armada_fb(state->fb)->mod);
|
||||
if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420)
|
||||
cfg |= CFG_PALETTE_ENA;
|
||||
if (state->visible)
|
||||
cfg |= CFG_GRA_ENA;
|
||||
if (dcrtc->interlaced)
|
||||
cfg |= CFG_GRA_FTOGGLE;
|
||||
cfg_mask = CFG_GRAFORMAT |
|
||||
CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
|
||||
CFG_SWAPYU | CFG_YUV2RGB) |
|
||||
CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
|
||||
CFG_GRA_ENA;
|
||||
} else if (old_state->visible != state->visible) {
|
||||
cfg = state->visible ? CFG_GRA_ENA : 0;
|
||||
cfg_mask = CFG_GRA_ENA;
|
||||
} else {
|
||||
cfg = cfg_mask = 0;
|
||||
}
|
||||
if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) ||
|
||||
drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) {
|
||||
cfg_mask |= CFG_GRA_HSMOOTH;
|
||||
if (drm_rect_width(&state->src) >> 16 !=
|
||||
drm_rect_width(&state->dst))
|
||||
cfg |= CFG_GRA_HSMOOTH;
|
||||
}
|
||||
|
||||
if (cfg_mask)
|
||||
armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
|
||||
LCD_SPU_DMA_CTRL0);
|
||||
|
||||
dcrtc->regs_idx += idx;
|
||||
}
|
||||
|
||||
static void armada_drm_primary_plane_atomic_disable(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state)
|
||||
{
|
||||
struct armada_crtc *dcrtc;
|
||||
struct armada_regs *regs;
|
||||
unsigned int idx = 0;
|
||||
|
||||
DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
|
||||
|
||||
if (!old_state->crtc)
|
||||
return;
|
||||
|
||||
DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n",
|
||||
plane->base.id, plane->name,
|
||||
old_state->crtc->base.id, old_state->crtc->name,
|
||||
old_state->fb->base.id);
|
||||
|
||||
dcrtc = drm_to_armada_crtc(old_state->crtc);
|
||||
regs = dcrtc->regs + dcrtc->regs_idx;
|
||||
|
||||
/* Disable plane and power down most RAMs and FIFOs */
|
||||
armada_reg_queue_mod(regs, idx, 0, CFG_GRA_ENA, LCD_SPU_DMA_CTRL0);
|
||||
armada_reg_queue_mod(regs, idx, CFG_PDWN256x32 | CFG_PDWN256x24 |
|
||||
CFG_PDWN256x8 | CFG_PDWN32x32 | CFG_PDWN64x66,
|
||||
0, LCD_SPU_SRAM_PARA1);
|
||||
|
||||
dcrtc->regs_idx += idx;
|
||||
}
|
||||
|
||||
static const struct drm_plane_helper_funcs armada_primary_plane_helper_funcs = {
|
||||
.prepare_fb = armada_drm_plane_prepare_fb,
|
||||
.cleanup_fb = armada_drm_plane_cleanup_fb,
|
||||
.atomic_check = armada_drm_plane_atomic_check,
|
||||
.atomic_update = armada_drm_primary_plane_atomic_update,
|
||||
.atomic_disable = armada_drm_primary_plane_atomic_disable,
|
||||
};
|
||||
|
||||
static const struct drm_plane_funcs armada_primary_plane_funcs = {
|
||||
.update_plane = drm_plane_helper_update,
|
||||
.disable_plane = drm_plane_helper_disable,
|
||||
.destroy = drm_primary_helper_destroy,
|
||||
.reset = drm_atomic_helper_plane_reset,
|
||||
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
|
||||
};
|
||||
|
||||
int armada_drm_plane_init(struct armada_plane *plane)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(plane->works); i++)
|
||||
plane->works[i].plane = &plane->base;
|
||||
|
||||
init_waitqueue_head(&plane->frame_wait);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int armada_drm_primary_plane_init(struct drm_device *drm,
|
||||
struct armada_plane *primary)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = armada_drm_plane_init(primary);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
drm_plane_helper_add(&primary->base,
|
||||
&armada_primary_plane_helper_funcs);
|
||||
|
||||
ret = drm_universal_plane_init(drm, &primary->base, 0,
|
||||
&armada_primary_plane_funcs,
|
||||
armada_primary_formats,
|
||||
ARRAY_SIZE(armada_primary_formats),
|
||||
NULL,
|
||||
DRM_PLANE_TYPE_PRIMARY, NULL);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#ifndef ARMADA_PLANE_H
|
||||
#define ARMADA_PLANE_H
|
||||
|
||||
void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
|
||||
int x, int y);
|
||||
int armada_drm_plane_prepare_fb(struct drm_plane *plane,
|
||||
struct drm_plane_state *state);
|
||||
void armada_drm_plane_cleanup_fb(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state);
|
||||
int armada_drm_plane_atomic_check(struct drm_plane *plane,
|
||||
struct drm_plane_state *state);
|
||||
int armada_drm_plane_init(struct armada_plane *plane);
|
||||
int armada_drm_primary_plane_init(struct drm_device *drm,
|
||||
struct armada_plane *primary);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue