MIPS: lantiq: implement support for FALCON soc
Adds support for the FALCON SoC. This SoC is from the FTTH/GPON SoC family. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3814/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
John Crispin
Ralf Baechle
parent
fa09eded0e
commit
d41ced01f2
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@ -0,0 +1,23 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
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*/
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#ifndef _FALCON_IRQ__
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#define _FALCON_IRQ__
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#define INT_NUM_IRQ0 8
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#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
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#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
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#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
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#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
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#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
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#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
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#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
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#define MIPS_CPU_TIMER_IRQ 7
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#endif /* _FALCON_IRQ__ */
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@ -0,0 +1,18 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
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*/
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#ifndef __FALCON_IRQ_H
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#define __FALCON_IRQ_H
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#include <falcon_irq.h>
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#define NR_IRQS 328
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#include_next <irq.h>
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#endif
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@ -0,0 +1,67 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _LTQ_FALCON_H__
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#define _LTQ_FALCON_H__
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#ifdef CONFIG_SOC_FALCON
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#include <linux/pinctrl/pinctrl.h>
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#include <lantiq.h>
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/* Chip IDs */
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#define SOC_ID_FALCON 0x01B8
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/* SoC Types */
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#define SOC_TYPE_FALCON 0x01
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/*
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* during early_printk no ioremap possible at this early stage
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* lets use KSEG1 instead
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*/
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#define LTQ_ASC0_BASE_ADDR 0x1E100C00
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#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
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/* WDT */
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#define LTQ_RST_CAUSE_WDTRST 0x0002
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/* CHIP ID */
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#define LTQ_STATUS_BASE_ADDR 0x1E802000
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#define FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
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#define FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
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#define FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
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/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
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#define SYSCTL_SYS1 0
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#define SYSCTL_SYSETH 1
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#define SYSCTL_SYSGPE 2
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/* BOOT_SEL - find what boot media we have */
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#define BS_FLASH 0x1
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#define BS_SPI 0x4
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/* global register ranges */
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extern __iomem void *ltq_ebu_membase;
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extern __iomem void *ltq_sys1_membase;
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#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
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#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
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#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y))
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#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x))
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#define ltq_sys1_w32_mask(clear, set, reg) \
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ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
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/*
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* to keep the irq code generic we need to define this to 0 as falcon
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* has no EIU/EBU
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*/
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#define LTQ_EBU_PCC_ISTAT 0
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#endif /* CONFIG_SOC_FALCON */
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#endif /* _LTQ_XWAY_H__ */
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@ -16,6 +16,10 @@ config SOC_XWAY
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bool "XWAY"
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select SOC_TYPE_XWAY
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select HW_HAS_PCI
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config SOC_FALCON
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bool "FALCON"
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endchoice
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choice
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@ -11,3 +11,4 @@ obj-y += dts/
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
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obj-$(CONFIG_SOC_FALCON) += falcon/
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@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/
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cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
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load-$(CONFIG_LANTIQ) = 0xffffffff80002000
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cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
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cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
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@ -0,0 +1 @@
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obj-y := prom.o reset.o sysctrl.o
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@ -0,0 +1,87 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
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* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <asm/io.h>
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#include <lantiq_soc.h>
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#include "../prom.h"
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#define SOC_FALCON "Falcon"
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#define SOC_FALCON_D "Falcon-D"
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#define SOC_FALCON_V "Falcon-V"
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#define SOC_FALCON_M "Falcon-M"
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#define COMP_FALCON "lantiq,falcon"
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#define PART_SHIFT 12
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#define PART_MASK 0x0FFFF000
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#define REV_SHIFT 28
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#define REV_MASK 0xF0000000
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#define SREV_SHIFT 22
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#define SREV_MASK 0x03C00000
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#define TYPE_SHIFT 26
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#define TYPE_MASK 0x3C000000
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/* reset, nmi and ejtag exception vectors */
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#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
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#define BOOT_RVEC (BOOT_REG_BASE | 0x00)
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#define BOOT_NVEC (BOOT_REG_BASE | 0x04)
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#define BOOT_EVEC (BOOT_REG_BASE | 0x08)
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void __init ltq_soc_nmi_setup(void)
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{
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extern void (*nmi_handler)(void);
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ltq_w32((unsigned long)&nmi_handler, (void *)BOOT_NVEC);
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}
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void __init ltq_soc_ejtag_setup(void)
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{
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extern void (*ejtag_debug_handler)(void);
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ltq_w32((unsigned long)&ejtag_debug_handler, (void *)BOOT_EVEC);
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}
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void __init ltq_soc_detect(struct ltq_soc_info *i)
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{
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u32 type;
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i->partnum = (ltq_r32(FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
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i->rev = (ltq_r32(FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
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i->srev = ((ltq_r32(FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT);
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i->compatible = COMP_FALCON;
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i->type = SOC_TYPE_FALCON;
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sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
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i->rev & 0x7, (i->srev & 0x3) + 1);
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switch (i->partnum) {
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case SOC_ID_FALCON:
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type = (ltq_r32(FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT;
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switch (type) {
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case 0:
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i->name = SOC_FALCON_D;
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break;
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case 1:
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i->name = SOC_FALCON_V;
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break;
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case 2:
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i->name = SOC_FALCON_M;
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break;
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default:
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i->name = SOC_FALCON;
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break;
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}
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break;
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default:
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unreachable();
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break;
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}
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}
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@ -0,0 +1,90 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
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* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/pm.h>
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#include <asm/reboot.h>
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#include <linux/export.h>
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#include <lantiq_soc.h>
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/* CPU0 Reset Source Register */
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#define SYS1_CPU0RS 0x0040
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/* reset cause mask */
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#define CPU0RS_MASK 0x0003
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/* CPU0 Boot Mode Register */
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#define SYS1_BM 0x00a0
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/* boot mode mask */
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#define BM_MASK 0x0005
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/* allow platform code to find out what surce we booted from */
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unsigned char ltq_boot_select(void)
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{
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return ltq_sys1_r32(SYS1_BM) & BM_MASK;
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}
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/* allow the watchdog driver to find out what the boot reason was */
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int ltq_reset_cause(void)
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{
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return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
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}
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EXPORT_SYMBOL_GPL(ltq_reset_cause);
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#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
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#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
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#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
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#define BOOT_PW1 0x4C545100
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#define BOOT_PW2 0x0051544C
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#define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
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#define WDT_PW1 0x00BE0000
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#define WDT_PW2 0x00DC0000
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static void machine_restart(char *command)
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{
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local_irq_disable();
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/* reboot magic */
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ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
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ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
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ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
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/* watchdog magic */
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ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
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ltq_w32(WDT_PW2 |
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(0x3 << 26) | /* PWL */
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(0x2 << 24) | /* CLKDIV */
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(0x1 << 31) | /* enable */
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(1), /* reload */
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(void *)WDT_REG_BASE);
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unreachable();
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}
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static void machine_halt(void)
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{
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local_irq_disable();
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unreachable();
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}
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static void machine_power_off(void)
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{
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local_irq_disable();
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unreachable();
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}
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static int __init mips_reboot_setup(void)
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{
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_machine_restart = machine_restart;
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_machine_halt = machine_halt;
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pm_power_off = machine_power_off;
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return 0;
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}
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arch_initcall(mips_reboot_setup);
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@ -0,0 +1,260 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
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* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/ioport.h>
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#include <linux/export.h>
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#include <linux/clkdev.h>
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#include <linux/of_address.h>
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#include <asm/delay.h>
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#include <lantiq_soc.h>
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#include "../clk.h"
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/* infrastructure control register */
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#define SYS1_INFRAC 0x00bc
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/* Configuration fuses for drivers and pll */
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#define STATUS_CONFIG 0x0040
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/* GPE frequency selection */
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#define GPPC_OFFSET 24
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#define GPEFREQ_MASK 0x00000C0
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#define GPEFREQ_OFFSET 10
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/* Clock status register */
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#define SYSCTL_CLKS 0x0000
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/* Clock enable register */
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#define SYSCTL_CLKEN 0x0004
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/* Clock clear register */
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#define SYSCTL_CLKCLR 0x0008
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/* Activation Status Register */
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#define SYSCTL_ACTS 0x0020
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/* Activation Register */
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#define SYSCTL_ACT 0x0024
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/* Deactivation Register */
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#define SYSCTL_DEACT 0x0028
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/* reboot Register */
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#define SYSCTL_RBT 0x002c
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/* CPU0 Clock Control Register */
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#define SYS1_CPU0CC 0x0040
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/* HRST_OUT_N Control Register */
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#define SYS1_HRSTOUTC 0x00c0
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/* clock divider bit */
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#define CPU0CC_CPUDIV 0x0001
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/* Activation Status Register */
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#define ACTS_ASC1_ACT 0x00000800
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#define ACTS_I2C_ACT 0x00004000
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#define ACTS_P0 0x00010000
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#define ACTS_P1 0x00010000
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#define ACTS_P2 0x00020000
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#define ACTS_P3 0x00020000
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#define ACTS_P4 0x00040000
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#define ACTS_PADCTRL0 0x00100000
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#define ACTS_PADCTRL1 0x00100000
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#define ACTS_PADCTRL2 0x00200000
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#define ACTS_PADCTRL3 0x00200000
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#define ACTS_PADCTRL4 0x00400000
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#define sysctl_w32(m, x, y) ltq_w32((x), sysctl_membase[m] + (y))
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#define sysctl_r32(m, x) ltq_r32(sysctl_membase[m] + (x))
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#define sysctl_w32_mask(m, clear, set, reg) \
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sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg)
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#define status_w32(x, y) ltq_w32((x), status_membase + (y))
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#define status_r32(x) ltq_r32(status_membase + (x))
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static void __iomem *sysctl_membase[3], *status_membase;
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void __iomem *ltq_sys1_membase, *ltq_ebu_membase;
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void falcon_trigger_hrst(int level)
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{
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sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC);
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}
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static inline void sysctl_wait(struct clk *clk,
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unsigned int test, unsigned int reg)
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{
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int err = 1000000;
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do {} while (--err && ((sysctl_r32(clk->module, reg)
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& clk->bits) != test));
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if (!err)
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pr_err("module de/activation failed %d %08X %08X %08X\n",
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clk->module, clk->bits, test,
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sysctl_r32(clk->module, reg) & clk->bits);
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}
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static int sysctl_activate(struct clk *clk)
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{
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sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
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sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
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sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
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return 0;
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}
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static void sysctl_deactivate(struct clk *clk)
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{
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sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
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sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT);
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sysctl_wait(clk, 0, SYSCTL_ACTS);
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}
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static int sysctl_clken(struct clk *clk)
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{
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sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
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sysctl_wait(clk, clk->bits, SYSCTL_CLKS);
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return 0;
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}
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static void sysctl_clkdis(struct clk *clk)
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{
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sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
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sysctl_wait(clk, 0, SYSCTL_CLKS);
|
||||
}
|
||||
|
||||
static void sysctl_reboot(struct clk *clk)
|
||||
{
|
||||
unsigned int act;
|
||||
unsigned int bits;
|
||||
|
||||
act = sysctl_r32(clk->module, SYSCTL_ACT);
|
||||
bits = ~act & clk->bits;
|
||||
if (bits != 0) {
|
||||
sysctl_w32(clk->module, bits, SYSCTL_CLKEN);
|
||||
sysctl_w32(clk->module, bits, SYSCTL_ACT);
|
||||
sysctl_wait(clk, bits, SYSCTL_ACTS);
|
||||
}
|
||||
sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT);
|
||||
sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
|
||||
}
|
||||
|
||||
/* enable the ONU core */
|
||||
static void falcon_gpe_enable(void)
|
||||
{
|
||||
unsigned int freq;
|
||||
unsigned int status;
|
||||
|
||||
/* if if the clock is already enabled */
|
||||
status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC);
|
||||
if (status & (1 << (GPPC_OFFSET + 1)))
|
||||
return;
|
||||
|
||||
if (status_r32(STATUS_CONFIG) == 0)
|
||||
freq = 1; /* use 625MHz on unfused chip */
|
||||
else
|
||||
freq = (status_r32(STATUS_CONFIG) &
|
||||
GPEFREQ_MASK) >>
|
||||
GPEFREQ_OFFSET;
|
||||
|
||||
/* apply new frequency */
|
||||
sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
|
||||
freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
|
||||
udelay(1);
|
||||
|
||||
/* enable new frequency */
|
||||
sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
static inline void clkdev_add_sys(const char *dev, unsigned int module,
|
||||
unsigned int bits)
|
||||
{
|
||||
struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
|
||||
|
||||
clk->cl.dev_id = dev;
|
||||
clk->cl.con_id = NULL;
|
||||
clk->cl.clk = clk;
|
||||
clk->module = module;
|
||||
clk->activate = sysctl_activate;
|
||||
clk->deactivate = sysctl_deactivate;
|
||||
clk->enable = sysctl_clken;
|
||||
clk->disable = sysctl_clkdis;
|
||||
clk->reboot = sysctl_reboot;
|
||||
clkdev_add(&clk->cl);
|
||||
}
|
||||
|
||||
void __init ltq_soc_init(void)
|
||||
{
|
||||
struct device_node *np_status =
|
||||
of_find_compatible_node(NULL, NULL, "lantiq,status-falcon");
|
||||
struct device_node *np_ebu =
|
||||
of_find_compatible_node(NULL, NULL, "lantiq,ebu-falcon");
|
||||
struct device_node *np_sys1 =
|
||||
of_find_compatible_node(NULL, NULL, "lantiq,sys1-falcon");
|
||||
struct device_node *np_syseth =
|
||||
of_find_compatible_node(NULL, NULL, "lantiq,syseth-falcon");
|
||||
struct device_node *np_sysgpe =
|
||||
of_find_compatible_node(NULL, NULL, "lantiq,sysgpe-falcon");
|
||||
struct resource res_status, res_ebu, res_sys[3];
|
||||
int i;
|
||||
|
||||
/* check if all the core register ranges are available */
|
||||
if (!np_status || !np_ebu || !np_sys1 || !np_syseth || !np_sysgpe)
|
||||
panic("Failed to load core nodes from devicetree");
|
||||
|
||||
if (of_address_to_resource(np_status, 0, &res_status) ||
|
||||
of_address_to_resource(np_ebu, 0, &res_ebu) ||
|
||||
of_address_to_resource(np_sys1, 0, &res_sys[0]) ||
|
||||
of_address_to_resource(np_syseth, 0, &res_sys[1]) ||
|
||||
of_address_to_resource(np_sysgpe, 0, &res_sys[2]))
|
||||
panic("Failed to get core resources");
|
||||
|
||||
if ((request_mem_region(res_status.start, resource_size(&res_status),
|
||||
res_status.name) < 0) ||
|
||||
(request_mem_region(res_ebu.start, resource_size(&res_ebu),
|
||||
res_ebu.name) < 0) ||
|
||||
(request_mem_region(res_sys[0].start,
|
||||
resource_size(&res_sys[0]),
|
||||
res_sys[0].name) < 0) ||
|
||||
(request_mem_region(res_sys[1].start,
|
||||
resource_size(&res_sys[1]),
|
||||
res_sys[1].name) < 0) ||
|
||||
(request_mem_region(res_sys[2].start,
|
||||
resource_size(&res_sys[2]),
|
||||
res_sys[2].name) < 0))
|
||||
pr_err("Failed to request core reources");
|
||||
|
||||
status_membase = ioremap_nocache(res_status.start,
|
||||
resource_size(&res_status));
|
||||
ltq_ebu_membase = ioremap_nocache(res_ebu.start,
|
||||
resource_size(&res_ebu));
|
||||
|
||||
if (!status_membase || !ltq_ebu_membase)
|
||||
panic("Failed to remap core resources");
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
sysctl_membase[i] = ioremap_nocache(res_sys[i].start,
|
||||
resource_size(&res_sys[i]));
|
||||
if (!sysctl_membase[i])
|
||||
panic("Failed to remap sysctrl resources");
|
||||
}
|
||||
ltq_sys1_membase = sysctl_membase[0];
|
||||
|
||||
falcon_gpe_enable();
|
||||
|
||||
/* get our 3 static rates for cpu, fpi and io clocks */
|
||||
if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
|
||||
clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
|
||||
else
|
||||
clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
|
||||
|
||||
/* add our clock domains */
|
||||
clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
|
||||
clkdev_add_sys("1d810100.gpio", SYSCTL_SYSETH, ACTS_P2);
|
||||
clkdev_add_sys("1e800100.gpio", SYSCTL_SYS1, ACTS_P1);
|
||||
clkdev_add_sys("1e800200.gpio", SYSCTL_SYS1, ACTS_P3);
|
||||
clkdev_add_sys("1e800300.gpio", SYSCTL_SYS1, ACTS_P4);
|
||||
clkdev_add_sys("1db01000.pad", SYSCTL_SYSETH, ACTS_PADCTRL0);
|
||||
clkdev_add_sys("1db02000.pad", SYSCTL_SYSETH, ACTS_PADCTRL2);
|
||||
clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1);
|
||||
clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3);
|
||||
clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4);
|
||||
clkdev_add_sys("1e100C00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
|
||||
clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
|
||||
}
|
||||
Loading…
Reference in New Issue