drm/radeon: set the full cache bit for fences on r7xx+
Needed to properly flush the read caches for fences. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -2706,14 +2706,17 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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struct radeon_fence *fence)
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{
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{
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
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PACKET3_SH_ACTION_ENA;
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if (rdev->family >= CHIP_RV770)
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cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
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if (rdev->wb.use_event) {
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if (rdev->wb.use_event) {
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u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
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u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
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/* flush read cache over gart */
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/* flush read cache over gart */
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radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
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radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
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radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
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radeon_ring_write(ring, cp_coher_cntl);
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PACKET3_VC_ACTION_ENA |
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PACKET3_SH_ACTION_ENA);
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radeon_ring_write(ring, 0xFFFFFFFF);
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radeon_ring_write(ring, 0xFFFFFFFF);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 10); /* poll interval */
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radeon_ring_write(ring, 10); /* poll interval */
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@ -2727,9 +2730,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
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} else {
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} else {
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/* flush read cache over gart */
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/* flush read cache over gart */
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radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
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radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
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radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
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radeon_ring_write(ring, cp_coher_cntl);
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PACKET3_VC_ACTION_ENA |
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PACKET3_SH_ACTION_ENA);
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radeon_ring_write(ring, 0xFFFFFFFF);
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radeon_ring_write(ring, 0xFFFFFFFF);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 10); /* poll interval */
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radeon_ring_write(ring, 10); /* poll interval */
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@ -1582,6 +1582,7 @@
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# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
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# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
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#define PACKET3_SURFACE_SYNC 0x43
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#define PACKET3_SURFACE_SYNC 0x43
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */
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# define PACKET3_TC_ACTION_ENA (1 << 23)
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# define PACKET3_TC_ACTION_ENA (1 << 23)
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# define PACKET3_VC_ACTION_ENA (1 << 24)
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# define PACKET3_VC_ACTION_ENA (1 << 24)
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# define PACKET3_CB_ACTION_ENA (1 << 25)
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# define PACKET3_CB_ACTION_ENA (1 << 25)
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