Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha
Pull alpha fixes from Matt Turner: "A build fix and a regression fix" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha: alpha/PCI: Fix noname IRQ level detection alpha: extend memset16 to EV6 optimised routines
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commit
d517bb79f4
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@ -102,6 +102,15 @@ sio_pci_route(void)
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alpha_mv.sys.sio.route_tab);
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}
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static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev)
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{
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if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
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(dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
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return false;
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return true;
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}
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static unsigned int __init
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sio_collect_irq_levels(void)
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{
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@ -110,8 +119,7 @@ sio_collect_irq_levels(void)
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/* Iterate through the devices, collecting IRQ levels. */
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for_each_pci_dev(dev) {
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if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
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(dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
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if (!sio_pci_dev_irq_needs_level(dev))
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continue;
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if (dev->irq)
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@ -120,8 +128,7 @@ sio_collect_irq_levels(void)
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return level_bits;
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}
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static void __init
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sio_fixup_irq_levels(unsigned int level_bits)
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static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset)
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{
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unsigned int old_level_bits;
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@ -139,12 +146,21 @@ sio_fixup_irq_levels(unsigned int level_bits)
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*/
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old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
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level_bits |= (old_level_bits & 0x71ff);
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if (reset)
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old_level_bits &= 0x71ff;
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level_bits |= old_level_bits;
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outb((level_bits >> 0) & 0xff, 0x4d0);
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outb((level_bits >> 8) & 0xff, 0x4d1);
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}
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static inline void
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sio_fixup_irq_levels(unsigned int level_bits)
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{
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__sio_fixup_irq_levels(level_bits, true);
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}
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static inline int
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noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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@ -181,7 +197,14 @@ noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
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int irq = COMMON_TABLE_LOOKUP, tmp;
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tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
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return irq >= 0 ? tmp : -1;
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irq = irq >= 0 ? tmp : -1;
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/* Fixup IRQ level if an actual IRQ mapping is detected */
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if (sio_pci_dev_irq_needs_level(dev) && irq >= 0)
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__sio_fixup_irq_levels(1 << irq, false);
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return irq;
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}
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static inline int
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@ -18,7 +18,7 @@
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* The algorithm for the leading and trailing quadwords remains the same,
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* however the loop has been unrolled to enable better memory throughput,
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* and the code has been replicated for each of the entry points: __memset
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* and __memsetw to permit better scheduling to eliminate the stalling
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* and __memset16 to permit better scheduling to eliminate the stalling
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* encountered during the mask replication.
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* A future enhancement might be to put in a byte store loop for really
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* small (say < 32 bytes) memset()s. Whether or not that change would be
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@ -34,7 +34,7 @@
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.globl memset
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.globl __memset
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.globl ___memset
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.globl __memsetw
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.globl __memset16
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.globl __constant_c_memset
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.ent ___memset
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@ -415,9 +415,9 @@ end:
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* to mask stalls. Note that entry point names also had to change
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*/
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.align 5
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.ent __memsetw
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.ent __memset16
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__memsetw:
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__memset16:
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.frame $30,0,$26,0
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.prologue 0
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@ -596,8 +596,8 @@ end_w:
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nop
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ret $31,($26),1 # L0 :
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.end __memsetw
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EXPORT_SYMBOL(__memsetw)
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.end __memset16
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EXPORT_SYMBOL(__memset16)
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memset = ___memset
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__memset = ___memset
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