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drm/nouveau/gr/gv100: initial support 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
hifive-unleashed-5.1
Ben Skeggs 2018-05-08 20:39:48 +10:00
parent 6e1f34e33c
commit d521097f58
12 changed files with 395 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/nouveau/include/nvif/class.h
View File

@ -155,6 +155,8 @@
#define PASCAL_A /* cl9097.h */ 0x0000c097
#define PASCAL_B /* cl9097.h */ 0x0000c197
#define VOLTA_A /* cl9097.h */ 0x0000c397
#define NV74_BSP 0x000074b0
#define GT212_MSVLD 0x000085b1
@ -194,6 +196,7 @@
#define MAXWELL_COMPUTE_B 0x0000b1c0
#define PASCAL_COMPUTE_A 0x0000c0c0
#define PASCAL_COMPUTE_B 0x0000c1c0
#define VOLTA_COMPUTE_A 0x0000c3c0
#define NV74_CIPHER 0x000074c1
#endif

1
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
View File

@ -48,4 +48,5 @@ int gp102_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gp104_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gp107_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gp10b_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gv100_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
#endif

4
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -2413,6 +2413,7 @@ nv140_chipset = {
.mmu = gv100_mmu_new,
.pci = gp100_pci_new,
.pmu = gp102_pmu_new,
.secboot = gp108_secboot_new,
.therm = gp100_therm_new,
.timer = gk20a_timer_new,
.top = gk104_top_new,
@ -2428,6 +2429,9 @@ nv140_chipset = {
.ce[8] = gv100_ce_new,
.dma = gv100_dma_new,
.fifo = gv100_fifo_new,
.gr = gv100_gr_new,
.nvdec = gp102_nvdec_new,
.sec2 = gp102_sec2_new,
};
static int

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
View File

@ -36,6 +36,7 @@ nvkm-y += nvkm/engine/gr/gp102.o
nvkm-y += nvkm/engine/gr/gp104.o
nvkm-y += nvkm/engine/gr/gp107.o
nvkm-y += nvkm/engine/gr/gp10b.o
nvkm-y += nvkm/engine/gr/gv100.o
nvkm-y += nvkm/engine/gr/ctxnv40.o
nvkm-y += nvkm/engine/gr/ctxnv50.o
@ -57,3 +58,4 @@ nvkm-y += nvkm/engine/gr/ctxgp100.o
nvkm-y += nvkm/engine/gr/ctxgp102.o
nvkm-y += nvkm/engine/gr/ctxgp104.o
nvkm-y += nvkm/engine/gr/ctxgp107.o
nvkm-y += nvkm/engine/gr/ctxgv100.o

10
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
View File

@ -1396,10 +1396,14 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_grctx_generate_floorsweep(gr);
if (grctx->r400088) grctx->r400088(gr, false);
if (gr->fuc_bundle)
gf100_gr_icmd(gr, gr->fuc_bundle);
else
gf100_gr_icmd(gr, grctx->icmd);
if (grctx->sw_veid_bundle_init)
gf100_gr_icmd(gr, grctx->sw_veid_bundle_init);
if (grctx->r400088) grctx->r400088(gr, true);
nvkm_wr32(device, 0x404154, idle_timeout);
@ -1448,6 +1452,9 @@ gf100_grctx_generate(struct gf100_gr *gr)
break;
);
if (grctx->unkn88c)
grctx->unkn88c(gr, true);
/* Reset FECS. */
nvkm_wr32(device, 0x409614, 0x00000070);
nvkm_usec(device, 10, NVKM_DELAY);
@ -1455,6 +1462,9 @@ gf100_grctx_generate(struct gf100_gr *gr)
nvkm_usec(device, 10, NVKM_DELAY);
nvkm_rd32(device, 0x409614);
if (grctx->unkn88c)
grctx->unkn88c(gr, false);
/* NV_PGRAPH_FE_PWR_MODE_AUTO. */
nvkm_wr32(device, 0x404170, 0x00000010);

5
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
View File

@ -21,6 +21,7 @@ void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int)
#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1)
struct gf100_grctx_func {
void (*unkn88c)(struct gf100_gr *, bool on);
/* main context generation function */
void (*main)(struct gf100_gr *, struct gf100_grctx *);
/* context-specific modify-on-first-load list generation function */
@ -35,6 +36,7 @@ struct gf100_grctx_func {
/* indirect context data, generated with icmds/mthds */
const struct gf100_gr_pack *icmd;
const struct gf100_gr_pack *mthd;
const struct gf100_gr_pack *sw_veid_bundle_init;
/* bundle circular buffer */
void (*bundle)(struct gf100_grctx *);
u32 bundle_size;
@ -66,6 +68,7 @@ struct gf100_grctx_func {
void (*tpc_mask)(struct gf100_gr *);
void (*smid_config)(struct gf100_gr *);
/* misc other things */
void (*r400088)(struct gf100_gr *, bool);
void (*r419cb8)(struct gf100_gr *);
void (*r418800)(struct gf100_gr *);
void (*r419eb0)(struct gf100_gr *);
@ -148,6 +151,8 @@ extern const struct gf100_grctx_func gp104_grctx;
extern const struct gf100_grctx_func gp107_grctx;
extern const struct gf100_grctx_func gv100_grctx;
/* context init value lists */
extern const struct gf100_gr_pack gf100_grctx_pack_icmd[];

215
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c 100644
View File

@ -0,0 +1,215 @@
/*
* Copyright 2018 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
static const struct gf100_gr_init
gv100_grctx_init_sw_veid_bundle_init_0[] = {
{ 0x00001000, 64, 0x00100000, 0x00000008 },
{ 0x00000941, 64, 0x00100000, 0x00000000 },
{ 0x0000097e, 64, 0x00100000, 0x00000000 },
{ 0x0000097f, 64, 0x00100000, 0x00000100 },
{ 0x0000035c, 64, 0x00100000, 0x00000000 },
{ 0x0000035d, 64, 0x00100000, 0x00000000 },
{ 0x00000a08, 64, 0x00100000, 0x00000000 },
{ 0x00000a09, 64, 0x00100000, 0x00000000 },
{ 0x00000a0a, 64, 0x00100000, 0x00000000 },
{ 0x00000352, 64, 0x00100000, 0x00000000 },
{ 0x00000353, 64, 0x00100000, 0x00000000 },
{ 0x00000358, 64, 0x00100000, 0x00000000 },
{ 0x00000359, 64, 0x00100000, 0x00000000 },
{ 0x00000370, 64, 0x00100000, 0x00000000 },
{ 0x00000371, 64, 0x00100000, 0x00000000 },
{ 0x00000372, 64, 0x00100000, 0x000fffff },
{ 0x00000366, 64, 0x00100000, 0x00000000 },
{ 0x00000367, 64, 0x00100000, 0x00000000 },
{ 0x00000368, 64, 0x00100000, 0x00000fff },
{ 0x00000623, 64, 0x00100000, 0x00000000 },
{ 0x00000624, 64, 0x00100000, 0x00000000 },
{ 0x0001e100, 1, 0x00000001, 0x02000001 },
{}
};
static const struct gf100_gr_pack
gv100_grctx_pack_sw_veid_bundle_init[] = {
{ gv100_grctx_init_sw_veid_bundle_init_0 },
{}
};
static void
gv100_grctx_generate_attrib(struct gf100_grctx *info)
{
struct gf100_gr *gr = info->gr;
const struct gf100_grctx_func *grctx = gr->func->grctx;
const u32 alpha = grctx->alpha_nr;
const u32 attrib = grctx->attrib_nr;
const u32 gfxp = grctx->gfxp_nr;
const int s = 12;
const int max_batches = 0xffff;
u32 size = grctx->alpha_nr_max * gr->tpc_total;
u32 ao = 0;
u32 bo = ao + size;
int gpc, ppc, b, n = 0;
size += grctx->gfxp_nr * gr->tpc_total;
size = ((size * 0x20) + 128) & ~127;
b = mmio_vram(info, size, (1 << s), false);
mmio_refn(info, 0x418810, 0x80000000, s, b);
mmio_refn(info, 0x419848, 0x10000000, s, b);
mmio_refn(info, 0x419c2c, 0x10000000, s, b);
mmio_refn(info, 0x419e00, 0x00000000, s, b);
mmio_wr32(info, 0x419e04, 0x80000000 | size >> 7);
mmio_wr32(info, 0x405830, attrib);
mmio_wr32(info, 0x40585c, alpha);
mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc];
const u32 gs = gfxp * gr->ppc_tpc_nr[gpc][ppc];
const u32 u = 0x418ea0 + (n * 0x04);
const u32 o = PPC_UNIT(gpc, ppc, 0);
if (!(gr->ppc_mask[gpc] & (1 << ppc)))
continue;
mmio_wr32(info, o + 0xc0, gs);
mmio_wr32(info, o + 0xf4, bo);
mmio_wr32(info, o + 0xf0, bs);
bo += gs;
mmio_wr32(info, o + 0xe4, as);
mmio_wr32(info, o + 0xf8, ao);
ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
mmio_wr32(info, u, bs);
}
}
mmio_wr32(info, 0x4181e4, 0x00000100);
mmio_wr32(info, 0x41befc, 0x00000100);
}
static void
gv100_grctx_generate_rop_mapping(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 data;
int i, j;
/* Pack tile map into register format. */
nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
gr->screen_tile_row_offset);
for (i = 0; i < 11; i++) {
for (data = 0, j = 0; j < 6; j++)
data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5);
nvkm_wr32(device, 0x418b08 + (i * 4), data);
nvkm_wr32(device, 0x41bf00 + (i * 4), data);
nvkm_wr32(device, 0x40780c + (i * 4), data);
}
/* GPC_BROADCAST.TP_BROADCAST */
nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
gr->screen_tile_row_offset);
for (i = 0, j = 1; i < 5; i++, j += 4) {
u8 v19 = (1 << (j + 0)) % gr->tpc_total;
u8 v20 = (1 << (j + 1)) % gr->tpc_total;
u8 v21 = (1 << (j + 2)) % gr->tpc_total;
u8 v22 = (1 << (j + 3)) % gr->tpc_total;
nvkm_wr32(device, 0x41bfb0 + (i * 4), (v22 << 24) |
(v21 << 16) |
(v20 << 8) |
v19);
}
/* UNK78xx */
nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
gr->screen_tile_row_offset);
}
static void
gv100_grctx_generate_r400088(struct gf100_gr *gr, bool on)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x400088, 0x00060000, on ? 0x00060000 : 0x00000000);
}
static void
gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
}
static void
gv100_grctx_generate_unkn(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);
nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);
nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);
nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
}
static void
gv100_grctx_unkn88c(struct gf100_gr *gr, bool on)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 mask = 0x00000010, data = on ? mask : 0x00000000;
nvkm_mask(device, 0x40988c, mask, data);
nvkm_rd32(device, 0x40988c);
nvkm_mask(device, 0x41a88c, mask, data);
nvkm_rd32(device, 0x41a88c);
nvkm_mask(device, 0x408a14, mask, data);
nvkm_rd32(device, 0x408a14);
}
const struct gf100_grctx_func
gv100_grctx = {
.unkn88c = gv100_grctx_unkn88c,
.main = gf100_grctx_generate_main,
.unkn = gv100_grctx_generate_unkn,
.sw_veid_bundle_init = gv100_grctx_pack_sw_veid_bundle_init,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x1680,
.pagepool = gp100_grctx_generate_pagepool,
.pagepool_size = 0x20000,
.attrib = gv100_grctx_generate_attrib,
.attrib_nr_max = 0x6c0,
.attrib_nr = 0x480,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
.gfxp_nr = 0xd10,
.sm_id = gv100_grctx_generate_sm_id,
.rop_mapping = gv100_grctx_generate_rop_mapping,
.dist_skip_table = gm200_grctx_generate_dist_skip_table,
.r406500 = gm200_grctx_generate_r406500,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.smid_config = gp100_grctx_generate_smid_config,
.r400088 = gv100_grctx_generate_r400088,
};

10
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -987,7 +987,7 @@ gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
}
static const struct nvkm_enum gf100_mp_warp_error[] = {
const struct nvkm_enum gf100_mp_warp_error[] = {
{ 0x01, "STACK_ERROR" },
{ 0x02, "API_STACK_ERROR" },
{ 0x03, "RET_EMPTY_STACK_ERROR" },
@ -1012,7 +1012,7 @@ static const struct nvkm_enum gf100_mp_warp_error[] = {
{}
};
static const struct nvkm_bitfield gf100_mp_global_error[] = {
const struct nvkm_bitfield gf100_mp_global_error[] = {
{ 0x00000001, "SM_TO_SM_FAULT" },
{ 0x00000002, "L1_ERROR" },
{ 0x00000004, "MULTIPLE_WARP_ERRORS" },
@ -2113,6 +2113,9 @@ gf100_gr_init(struct gf100_gr *gr)
struct nvkm_device *device = gr->base.engine.subdev.device;
int gpc, tpc, rop;
if (gr->func->init_419bd8)
gr->func->init_419bd8(gr);
gr->func->init_gpc_mmu(gr);
if (gr->fuc_sw_nonctx)
@ -2213,6 +2216,9 @@ gf100_gr_init(struct gf100_gr *gr)
gf100_gr_zbc_init(gr);
if (gr->func->init_4188a4)
gr->func->init_4188a4(gr);
return gf100_gr_init_ctxctl(gr);
}

6
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@ -149,6 +149,7 @@ struct gf100_gr_func {
void (*oneinit_tiles)(struct gf100_gr *);
void (*oneinit_sm_id)(struct gf100_gr *);
int (*init)(struct gf100_gr *);
void (*init_419bd8)(struct gf100_gr *);
void (*init_gpc_mmu)(struct gf100_gr *);
void (*init_r405a14)(struct gf100_gr *);
void (*init_bios)(struct gf100_gr *);
@ -170,6 +171,7 @@ struct gf100_gr_func {
void (*init_504430)(struct gf100_gr *, int gpc, int tpc);
void (*init_shader_exceptions)(struct gf100_gr *, int gpc, int tpc);
void (*init_400054)(struct gf100_gr *);
void (*init_4188a4)(struct gf100_gr *);
void (*trap_mp)(struct gf100_gr *, int gpc, int tpc);
void (*set_hww_esr_report_mask)(struct gf100_gr *);
const struct gf100_gr_pack *mmio;
@ -266,7 +268,7 @@ extern const struct nvkm_object_func gf100_fermi;
struct gf100_gr_init {
u32 addr;
u8 count;
u8 pitch;
u32 pitch;
u32 data;
};
@ -337,6 +339,8 @@ extern const struct gf100_gr_init gf100_gr_init_fe_1[];
extern const struct gf100_gr_init gf100_gr_init_pe_1[];
void gf100_gr_init_gpc_mmu(struct gf100_gr *);
void gf100_gr_trap_mp(struct gf100_gr *, int, int);
extern const struct nvkm_bitfield gf100_mp_global_error[];
extern const struct nvkm_enum gf100_mp_warp_error[];
extern const struct gf100_gr_init gf104_gr_init_ds_0[];
extern const struct gf100_gr_init gf104_gr_init_tex_0[];

120
drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c 100644
View File

@ -0,0 +1,120 @@
/*
* Copyright 2018 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
static void
gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730));
u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734));
const struct nvkm_enum *warp;
char glob[128];
nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
nvkm_error(subdev, "GPC%i/TPC%i/MP trap: "
"global %08x [%s] warp %04x [%s]\n",
gpc, tpc, gerr, glob, werr, warp ? warp->name : "");
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730), 0x00000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734), gerr);
}
static void
gv100_gr_init_4188a4(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x4188a4, 0x03000000, 0x03000000);
}
static void
gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int sm;
for (sm = 0; sm < 0x100; sm += 0x80) {
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x728 + sm), 0x0085eb64);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x610), 0x00000001);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x72c + sm), 0x00000004);
}
}
static void
gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0x403f0000);
}
static void
gv100_gr_init_419bd8(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x419bd8, 0x00000700, 0x00000000);
}
static const struct gf100_gr_func
gv100_gr = {
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gm200_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_419bd8 = gv100_gr_init_419bd8,
.init_gpc_mmu = gm200_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_504430 = gv100_gr_init_504430,
.init_shader_exceptions = gv100_gr_init_shader_exceptions,
.init_4188a4 = gv100_gr_init_4188a4,
.trap_mp = gv100_gr_trap_mp,
.rops = gm200_gr_rops,
.gpc_nr = 6,
.tpc_nr = 5,
.ppc_nr = 3,
.grctx = &gv100_grctx,
.zbc = &gp102_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, VOLTA_A, &gf100_fermi },
{ -1, -1, VOLTA_COMPUTE_A },
{}
}
};
int
gv100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
{
return gm200_gr_new_(&gv100_gr, device, index, pgr);
}

1
drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c
View File

@ -506,6 +506,7 @@ nvkm_msgqueue_new(u32 version, struct nvkm_falcon *falcon,
break;
case 0x0148cdec:
case 0x015ccf3e:
case 0x0167d263:
ret = msgqueue_0148cdec_new(falcon, sb, queue);
break;
default:

21
drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c
View File

@ -65,3 +65,24 @@ MODULE_FIRMWARE("nvidia/gp108/nvdec/scrubber.bin");
MODULE_FIRMWARE("nvidia/gp108/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/gp108/sec2/image.bin");
MODULE_FIRMWARE("nvidia/gp108/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/gv100/acr/bl.bin");
MODULE_FIRMWARE("nvidia/gv100/acr/unload_bl.bin");
MODULE_FIRMWARE("nvidia/gv100/acr/ucode_load.bin");
MODULE_FIRMWARE("nvidia/gv100/acr/ucode_unload.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/gv100/nvdec/scrubber.bin");
MODULE_FIRMWARE("nvidia/gv100/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/gv100/sec2/image.bin");
MODULE_FIRMWARE("nvidia/gv100/sec2/sig.bin");