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drm/i915: POSTING_READ the new rps value 

In order to keep our cached values in sync with the hardware, we need a
posting read here.

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
hifive-unleashed-5.1
Ben Widawsky 2012-09-07 19:43:41 -07:00 committed by Daniel Vetter
parent df6eedc81d
commit d5570a7243
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/i915/intel_pm.c
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@ -2338,6 +2338,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
*/
I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
POSTING_READ(GEN6_RPNSWREQ);
dev_priv->rps.cur_delay = val;
trace_intel_gpu_freq_change(val * 50);