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MLK-23618-11: ASoC: fsl_spdif: Don't bind clock with regmap 

The call flow:
devm_regmap_init_mmio_clk
   - clk_prepare()
      - clk_pm_runtime_get()

Cause the power domain of lpcg clock always be enabled.
which impact the power consumption.

So we can't bind clock with regmap, then explicitly enable
clock when using. As we already enable all clock in
pm_runtime_resume, so only need to enable clock in probe.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Shengjiu Wang 2020-03-17 18:27:37 +08:00
parent d91068f322
commit d55d453fdf
1 changed files with 8 additions and 2 deletions
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10
sound/soc/fsl/fsl_spdif.c
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@ -1392,7 +1392,7 @@ static int fsl_spdif_probe(struct platform_device *pdev)
return PTR_ERR(regs);
spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
"core", regs, &fsl_spdif_regmap_config);
NULL, regs, &fsl_spdif_regmap_config);
if (IS_ERR(spdif_priv->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(spdif_priv->regmap);
@ -1494,10 +1494,16 @@ static int fsl_spdif_probe(struct platform_device *pdev)
spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
/*Clear the val bit for Tx*/
ret = clk_prepare_enable(spdif_priv->coreclk);
if (ret)
return ret;
/*Cleer the val bit for Tx*/
regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SCR,
SCR_VAL_MASK, 1 << SCR_VAL_OFFSET);
clk_disable_unprepare(spdif_priv->coreclk);
pm_runtime_enable(&pdev->dev);
/* Register with ASoC */