mlxsw: reg: Add Router Algorithmic LPM Unicast Entry Register definition
Serves for adding, updating and removing fib entries. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Jiri Pirko
David S. Miller
parent
6b75c4807d
commit
d5a1c749d2
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@ -3622,6 +3622,268 @@ static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
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mlxsw_reg_raltb_tree_id_set(payload, tree_id);
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}
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/* RALUE - Router Algorithmic LPM Unicast Entry Register
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* -----------------------------------------------------
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* RALUE is used to configure and query LPM entries that serve
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* the Unicast protocols.
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*/
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#define MLXSW_REG_RALUE_ID 0x8013
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#define MLXSW_REG_RALUE_LEN 0x38
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static const struct mlxsw_reg_info mlxsw_reg_ralue = {
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.id = MLXSW_REG_RALUE_ID,
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.len = MLXSW_REG_RALUE_LEN,
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};
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/* reg_ralue_protocol
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* Protocol.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
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enum mlxsw_reg_ralue_op {
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/* Read operation. If entry doesn't exist, the operation fails. */
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MLXSW_REG_RALUE_OP_QUERY_READ = 0,
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/* Clear on read operation. Used to read entry and
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* clear Activity bit.
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*/
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MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
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/* Write operation. Used to write a new entry to the table. All RW
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* fields are written for new entry. Activity bit is set
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* for new entries.
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*/
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MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
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/* Update operation. Used to update an existing route entry and
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* only update the RW fields that are detailed in the field
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* op_u_mask. If entry doesn't exist, the operation fails.
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*/
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MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
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/* Clear activity. The Activity bit (the field a) is cleared
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* for the entry.
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*/
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MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
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/* Delete operation. Used to delete an existing entry. If entry
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* doesn't exist, the operation fails.
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*/
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MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
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};
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/* reg_ralue_op
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* Operation.
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* Access: OP
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*/
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MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
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/* reg_ralue_a
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* Activity. Set for new entries. Set if a packet lookup has hit on the
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* specific entry, only if the entry is a route. To clear the a bit, use
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* "clear activity" op.
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* Enabled by activity_dis in RGCR
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* Access: RO
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*/
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MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
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/* reg_ralue_virtual_router
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* Virtual Router ID
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* Range is 0..cap_max_virtual_routers-1
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* Access: Index
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*/
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MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
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#define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
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#define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
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#define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
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/* reg_ralue_op_u_mask
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* opcode update mask.
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* On read operation, this field is reserved.
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* This field is valid for update opcode, otherwise - reserved.
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* This field is a bitmask of the fields that should be updated.
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* Access: WO
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*/
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MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
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/* reg_ralue_prefix_len
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* Number of bits in the prefix of the LPM route.
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* Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
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* two entries in the physical HW table.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
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/* reg_ralue_dip*
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* The prefix of the route or of the marker that the object of the LPM
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* is compared with. The most significant bits of the dip are the prefix.
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* The list significant bits must be '0' if the prefix_len is smaller
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* than 128 for IPv6 or smaller than 32 for IPv4.
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* IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
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enum mlxsw_reg_ralue_entry_type {
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MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
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MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
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MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
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};
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/* reg_ralue_entry_type
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* Entry type.
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* Note - for Marker entries, the action_type and action fields are reserved.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
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/* reg_ralue_bmp_len
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* The best match prefix length in the case that there is no match for
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* longer prefixes.
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* If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
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* Note for any update operation with entry_type modification this
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* field must be set.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
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enum mlxsw_reg_ralue_action_type {
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MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
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MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
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MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
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};
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/* reg_ralue_action_type
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* Action Type
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* Indicates how the IP address is connected.
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* It can be connected to a local subnet through local_erif or can be
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* on a remote subnet connected through a next-hop router,
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* or transmitted to the CPU.
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* Reserved when entry_type = MARKER_ENTRY
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
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enum mlxsw_reg_ralue_trap_action {
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MLXSW_REG_RALUE_TRAP_ACTION_NOP,
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MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
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MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
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MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
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MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
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};
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/* reg_ralue_trap_action
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* Trap action.
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* For IP2ME action, only NOP and MIRROR are possible.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
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/* reg_ralue_trap_id
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* Trap ID to be reported to CPU.
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* Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
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* For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
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/* reg_ralue_adjacency_index
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* Points to the first entry of the group-based ECMP.
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* Only relevant in case of REMOTE action.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
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/* reg_ralue_ecmp_size
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* Amount of sequential entries starting
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* from the adjacency_index (the number of ECMPs).
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* The valid range is 1-64, 512, 1024, 2048 and 4096.
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* Reserved when trap_action is TRAP or DISCARD_ERROR.
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* Only relevant in case of REMOTE action.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
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/* reg_ralue_local_erif
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* Egress Router Interface.
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* Only relevant in case of LOCAL action.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
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/* reg_ralue_v
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* Valid bit for the tunnel_ptr field.
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* If valid = 0 then trap to CPU as IP2ME trap ID.
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* If valid = 1 and the packet format allows NVE or IPinIP tunnel
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* decapsulation then tunnel decapsulation is done.
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* If valid = 1 and packet format does not allow NVE or IPinIP tunnel
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* decapsulation then trap as IP2ME trap ID.
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* Only relevant in case of IP2ME action.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ralue, v, 0x24, 31, 1);
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/* reg_ralue_tunnel_ptr
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* Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
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* For Spectrum, pointer to KVD Linear.
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* Only relevant in case of IP2ME action.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ralue, tunnel_ptr, 0x24, 0, 24);
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static inline void mlxsw_reg_ralue_pack(char *payload,
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enum mlxsw_reg_ralxx_protocol protocol,
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enum mlxsw_reg_ralue_op op,
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u16 virtual_router, u8 prefix_len)
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{
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MLXSW_REG_ZERO(ralue, payload);
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mlxsw_reg_ralue_protocol_set(payload, protocol);
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mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
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mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
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mlxsw_reg_ralue_entry_type_set(payload,
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MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
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mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
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}
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static inline void mlxsw_reg_ralue_pack4(char *payload,
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enum mlxsw_reg_ralxx_protocol protocol,
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enum mlxsw_reg_ralue_op op,
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u16 virtual_router, u8 prefix_len,
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u32 dip)
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{
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mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
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mlxsw_reg_ralue_dip4_set(payload, dip);
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}
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static inline void
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mlxsw_reg_ralue_act_remote_pack(char *payload,
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enum mlxsw_reg_ralue_trap_action trap_action,
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u16 trap_id, u32 adjacency_index, u16 ecmp_size)
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{
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mlxsw_reg_ralue_action_type_set(payload,
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MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
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mlxsw_reg_ralue_trap_action_set(payload, trap_action);
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mlxsw_reg_ralue_trap_id_set(payload, trap_id);
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mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
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mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
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}
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static inline void
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mlxsw_reg_ralue_act_local_pack(char *payload,
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enum mlxsw_reg_ralue_trap_action trap_action,
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u16 trap_id, u16 local_erif)
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{
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mlxsw_reg_ralue_action_type_set(payload,
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MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
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mlxsw_reg_ralue_trap_action_set(payload, trap_action);
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mlxsw_reg_ralue_trap_id_set(payload, trap_id);
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mlxsw_reg_ralue_local_erif_set(payload, local_erif);
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}
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static inline void
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mlxsw_reg_ralue_act_ip2me_pack(char *payload)
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{
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mlxsw_reg_ralue_action_type_set(payload,
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MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
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}
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/* MFCR - Management Fan Control Register
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* --------------------------------------
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* This register controls the settings of the Fan Speed PWM mechanism.
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@ -4370,6 +4632,8 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
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return "RALST";
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case MLXSW_REG_RALTB_ID:
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return "RALTB";
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case MLXSW_REG_RALUE_ID:
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return "RALUE";
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case MLXSW_REG_MFCR_ID:
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return "MFCR";
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case MLXSW_REG_MFSC_ID:
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