powerpc/85xx: Add support for SMP initialization
Added 85xx specifc smp_ops structure. We use ePAPR style boot release and the MPIC for IPIs at this point. Additionally added routines for secondary cpu entry and initializtion. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Trent Piepho <tpiepho@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>hifive-unleashed-5.1
Kumar Gala
parent
06b90969a7
commit
d5b26db2cf
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@ -92,6 +92,7 @@ _ENTRY(_start);
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* if needed
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*/
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_ENTRY(__early_start)
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/* 1. Find the index of the entry we're executing in */
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bl invstr /* Find our address */
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invstr: mflr r6 /* Make it accessible */
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@ -348,6 +349,15 @@ skpinv: addi r6,r6,1 /* Increment */
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mtspr SPRN_DBSR,r2
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#endif
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#ifdef CONFIG_SMP
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/* Check to see if we're the second processor, and jump
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* to the secondary_start code if so
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*/
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mfspr r24,SPRN_PIR
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cmpwi r24,0
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bne __secondary_start
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#endif
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/*
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* This is where the main kernel code starts.
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*/
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@ -739,6 +749,9 @@ finish_tlb_load:
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rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */
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#else
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rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
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#endif
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#ifdef CONFIG_SMP
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ori r12, r12, MAS2_M
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#endif
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mtspr SPRN_MAS2, r12
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@ -1042,6 +1055,63 @@ _GLOBAL(flush_dcache_L1)
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blr
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#ifdef CONFIG_SMP
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/* When we get here, r24 needs to hold the CPU # */
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.globl __secondary_start
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__secondary_start:
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lis r3,__secondary_hold_acknowledge@h
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ori r3,r3,__secondary_hold_acknowledge@l
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stw r24,0(r3)
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li r3,0
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mr r4,r24 /* Why? */
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bl call_setup_cpu
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lis r3,tlbcam_index@ha
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lwz r3,tlbcam_index@l(r3)
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mtctr r3
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li r26,0 /* r26 safe? */
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/* Load each CAM entry */
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1: mr r3,r26
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bl loadcam_entry
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addi r26,r26,1
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bdnz 1b
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/* get current_thread_info and current */
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lis r1,secondary_ti@ha
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lwz r1,secondary_ti@l(r1)
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lwz r2,TI_TASK(r1)
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/* stack */
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addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
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li r0,0
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stw r0,0(r1)
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/* ptr to current thread */
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addi r4,r2,THREAD /* address of our thread_struct */
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mtspr SPRN_SPRG3,r4
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/* Setup the defaults for TLB entries */
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li r4,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
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mtspr SPRN_MAS4,r4
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/* Jump to start_secondary */
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lis r4,MSR_KERNEL@h
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ori r4,r4,MSR_KERNEL@l
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lis r3,start_secondary@h
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ori r3,r3,start_secondary@l
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mtspr SPRN_SRR0,r3
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mtspr SPRN_SRR1,r4
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sync
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rfi
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sync
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.globl __secondary_hold_acknowledge
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__secondary_hold_acknowledge:
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.long -1
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#endif
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/*
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* We put a few things here that have to be page-aligned. This stuff
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* goes at the beginning of the data segment, which is page-aligned.
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@ -1,6 +1,8 @@
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#
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# Makefile for the PowerPC 85xx linux kernel.
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#
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
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obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
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obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
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@ -0,0 +1,104 @@
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/*
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* Author: Andy Fleming <afleming@freescale.com>
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* Kumar Gala <galak@kernel.crashing.org>
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*
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* Copyright 2006-2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <asm/machdep.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/mpic.h>
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#include <asm/cacheflush.h>
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#include <sysdev/fsl_soc.h>
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extern volatile unsigned long __secondary_hold_acknowledge;
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extern void __early_start(void);
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#define BOOT_ENTRY_ADDR_UPPER 0
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#define BOOT_ENTRY_ADDR_LOWER 1
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#define BOOT_ENTRY_R3_UPPER 2
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#define BOOT_ENTRY_R3_LOWER 3
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#define BOOT_ENTRY_RESV 4
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#define BOOT_ENTRY_PIR 5
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#define BOOT_ENTRY_R6_UPPER 6
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#define BOOT_ENTRY_R6_LOWER 7
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#define NUM_BOOT_ENTRY 8
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#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))
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static void __init
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smp_85xx_kick_cpu(int nr)
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{
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unsigned long flags;
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const u64 *cpu_rel_addr;
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__iomem u32 *bptr_vaddr;
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struct device_node *np;
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int n = 0;
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WARN_ON (nr < 0 || nr >= NR_CPUS);
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pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);
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local_irq_save(flags);
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np = of_get_cpu_node(nr, NULL);
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cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
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if (cpu_rel_addr == NULL) {
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printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
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return;
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}
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/* Map the spin table */
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bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY);
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out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr);
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out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start));
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/* Wait a bit for the CPU to ack. */
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while ((__secondary_hold_acknowledge != nr) && (++n < 1000))
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mdelay(1);
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iounmap(bptr_vaddr);
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local_irq_restore(flags);
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pr_debug("waited %d msecs for CPU #%d.\n", n, nr);
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}
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static void __init
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smp_85xx_setup_cpu(int cpu_nr)
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{
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mpic_setup_this_cpu();
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/* Clear any pending timer interrupts */
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mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
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/* Enable decrementer interrupt */
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mtspr(SPRN_TCR, TCR_DIE);
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}
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struct smp_ops_t smp_85xx_ops = {
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.message_pass = smp_mpic_message_pass,
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.probe = smp_mpic_probe,
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.kick_cpu = smp_85xx_kick_cpu,
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.setup_cpu = smp_85xx_setup_cpu,
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};
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void __init
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mpc85xx_smp_init(void)
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{
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smp_ops = &smp_85xx_ops;
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}
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