drm/amdgpu: Skip some registers config for SRIOV
Some registers are not accessible to virtual function setup, so skip their initialization when in VF-SRIOV mode. v2: move SRIOV VF check into specify functions; modify commit description and comment. Signed-off-by: Liu ChengZhe <ChengZhe.Liu@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>zero-sugar-mainline-defconfig
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78484d7c74
commit
d5bbb4761c
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@ -135,6 +135,12 @@ static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
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{
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uint32_t tmp;
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/* These registers are not accessible to VF-SRIOV.
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* The PF will program them instead.
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*/
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if (amdgpu_sriov_vf(adev))
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return;
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/* Setup L2 cache */
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tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
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tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
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@ -190,6 +196,12 @@ static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
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static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
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{
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/* These registers are not accessible to VF-SRIOV.
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* The PF will program them instead.
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*/
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if (amdgpu_sriov_vf(adev))
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return;
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WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
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0xFFFFFFFF);
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WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
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@ -326,6 +338,13 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
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bool value)
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{
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u32 tmp;
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/* These registers are not accessible to VF-SRIOV.
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* The PF will program them instead.
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*/
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if (amdgpu_sriov_vf(adev))
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return;
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tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
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tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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@ -134,6 +134,12 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
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{
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uint32_t tmp;
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/* These registers are not accessible to VF-SRIOV.
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* The PF will program them instead.
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*/
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if (amdgpu_sriov_vf(adev))
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return;
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/* Setup L2 cache */
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tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
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@ -189,6 +195,12 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
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static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
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{
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/* These registers are not accessible to VF-SRIOV.
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* The PF will program them instead.
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*/
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if (amdgpu_sriov_vf(adev))
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return;
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WREG32_SOC15(MMHUB, 0,
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mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
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0xFFFFFFFF);
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@ -318,6 +330,13 @@ void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
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void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
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{
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u32 tmp;
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/* These registers are not accessible to VF-SRIOV.
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* The PF will program them instead.
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*/
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if (amdgpu_sriov_vf(adev))
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return;
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tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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