drm/radeon/kms: add support for Llano Fusion APUs
- add gpu init support - add blit support - add ucode loader Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1433,6 +1433,8 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
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case CHIP_CEDAR:
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case CHIP_REDWOOD:
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case CHIP_PALM:
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case CHIP_SUMO:
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case CHIP_SUMO2:
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case CHIP_TURKS:
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case CHIP_CAICOS:
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force_no_swizzle = false;
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@ -1562,6 +1564,8 @@ static void evergreen_program_channel_remap(struct radeon_device *rdev)
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case CHIP_REDWOOD:
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case CHIP_CEDAR:
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case CHIP_PALM:
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case CHIP_SUMO:
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case CHIP_SUMO2:
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case CHIP_TURKS:
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case CHIP_CAICOS:
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default:
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@ -1703,6 +1707,54 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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rdev->config.evergreen.max_hw_contexts = 4;
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rdev->config.evergreen.sq_num_cf_insts = 1;
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rdev->config.evergreen.sc_prim_fifo_size = 0x40;
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rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
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rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
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break;
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case CHIP_SUMO:
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rdev->config.evergreen.num_ses = 1;
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rdev->config.evergreen.max_pipes = 4;
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rdev->config.evergreen.max_tile_pipes = 2;
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if (rdev->pdev->device == 0x9648)
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rdev->config.evergreen.max_simds = 3;
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else if ((rdev->pdev->device == 0x9647) ||
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(rdev->pdev->device == 0x964a))
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rdev->config.evergreen.max_simds = 4;
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else
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rdev->config.evergreen.max_simds = 5;
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rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
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rdev->config.evergreen.max_gprs = 256;
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rdev->config.evergreen.max_threads = 248;
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rdev->config.evergreen.max_gs_threads = 32;
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rdev->config.evergreen.max_stack_entries = 256;
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rdev->config.evergreen.sx_num_of_sets = 4;
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rdev->config.evergreen.sx_max_export_size = 256;
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rdev->config.evergreen.sx_max_export_pos_size = 64;
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rdev->config.evergreen.sx_max_export_smx_size = 192;
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rdev->config.evergreen.max_hw_contexts = 8;
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rdev->config.evergreen.sq_num_cf_insts = 2;
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rdev->config.evergreen.sc_prim_fifo_size = 0x40;
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rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
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rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
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break;
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case CHIP_SUMO2:
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rdev->config.evergreen.num_ses = 1;
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rdev->config.evergreen.max_pipes = 4;
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rdev->config.evergreen.max_tile_pipes = 4;
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rdev->config.evergreen.max_simds = 2;
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rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
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rdev->config.evergreen.max_gprs = 256;
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rdev->config.evergreen.max_threads = 248;
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rdev->config.evergreen.max_gs_threads = 32;
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rdev->config.evergreen.max_stack_entries = 512;
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rdev->config.evergreen.sx_num_of_sets = 4;
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rdev->config.evergreen.sx_max_export_size = 256;
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rdev->config.evergreen.sx_max_export_pos_size = 64;
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rdev->config.evergreen.sx_max_export_smx_size = 192;
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rdev->config.evergreen.max_hw_contexts = 8;
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rdev->config.evergreen.sq_num_cf_insts = 2;
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rdev->config.evergreen.sc_prim_fifo_size = 0x40;
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rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
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rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
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@ -2054,6 +2106,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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switch (rdev->family) {
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case CHIP_CEDAR:
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case CHIP_PALM:
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case CHIP_SUMO:
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case CHIP_SUMO2:
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case CHIP_CAICOS:
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/* no vertex cache */
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sq_config &= ~VC_ENABLE;
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@ -2075,6 +2129,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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switch (rdev->family) {
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case CHIP_CEDAR:
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case CHIP_PALM:
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case CHIP_SUMO:
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case CHIP_SUMO2:
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ps_thread_count = 96;
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break;
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default:
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@ -2114,6 +2170,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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switch (rdev->family) {
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case CHIP_CEDAR:
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case CHIP_PALM:
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case CHIP_SUMO:
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case CHIP_SUMO2:
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case CHIP_CAICOS:
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vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
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break;
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@ -153,6 +153,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
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if ((rdev->family == CHIP_CEDAR) ||
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(rdev->family == CHIP_PALM) ||
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(rdev->family == CHIP_SUMO) ||
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(rdev->family == CHIP_SUMO2) ||
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(rdev->family == CHIP_CAICOS))
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, 48, gpu_addr);
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@ -379,6 +381,48 @@ set_default_state(struct radeon_device *rdev)
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num_hs_stack_entries = 42;
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num_ls_stack_entries = 42;
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break;
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case CHIP_SUMO:
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num_ps_gprs = 93;
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num_vs_gprs = 46;
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num_temp_gprs = 4;
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num_gs_gprs = 31;
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num_es_gprs = 31;
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num_hs_gprs = 23;
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num_ls_gprs = 23;
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num_ps_threads = 96;
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num_vs_threads = 25;
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num_gs_threads = 25;
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num_es_threads = 25;
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num_hs_threads = 25;
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num_ls_threads = 25;
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num_ps_stack_entries = 42;
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num_vs_stack_entries = 42;
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num_gs_stack_entries = 42;
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num_es_stack_entries = 42;
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num_hs_stack_entries = 42;
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num_ls_stack_entries = 42;
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break;
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case CHIP_SUMO2:
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num_ps_gprs = 93;
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num_vs_gprs = 46;
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num_temp_gprs = 4;
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num_gs_gprs = 31;
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num_es_gprs = 31;
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num_hs_gprs = 23;
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num_ls_gprs = 23;
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num_ps_threads = 96;
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num_vs_threads = 25;
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num_gs_threads = 25;
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num_es_threads = 25;
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num_hs_threads = 25;
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num_ls_threads = 25;
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num_ps_stack_entries = 85;
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num_vs_stack_entries = 85;
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num_gs_stack_entries = 85;
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num_es_stack_entries = 85;
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num_hs_stack_entries = 85;
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num_ls_stack_entries = 85;
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break;
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case CHIP_BARTS:
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num_ps_gprs = 93;
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num_vs_gprs = 46;
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@ -446,6 +490,8 @@ set_default_state(struct radeon_device *rdev)
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if ((rdev->family == CHIP_CEDAR) ||
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(rdev->family == CHIP_PALM) ||
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(rdev->family == CHIP_SUMO) ||
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(rdev->family == CHIP_SUMO2) ||
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(rdev->family == CHIP_CAICOS))
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sq_config = 0;
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else
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@ -87,6 +87,10 @@ MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
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MODULE_FIRMWARE("radeon/PALM_pfp.bin");
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MODULE_FIRMWARE("radeon/PALM_me.bin");
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MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
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MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
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MODULE_FIRMWARE("radeon/SUMO_me.bin");
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MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
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MODULE_FIRMWARE("radeon/SUMO2_me.bin");
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int r600_debugfs_mc_info_init(struct radeon_device *rdev);
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@ -2024,6 +2028,14 @@ int r600_init_microcode(struct radeon_device *rdev)
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chip_name = "PALM";
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rlc_chip_name = "SUMO";
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break;
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case CHIP_SUMO:
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chip_name = "SUMO";
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rlc_chip_name = "SUMO";
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break;
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case CHIP_SUMO2:
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chip_name = "SUMO2";
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rlc_chip_name = "SUMO";
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break;
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default: BUG();
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}
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