drm/i915: Ensure all PLL registers are flushed before a udelay()
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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c64e311e65
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@ -1641,6 +1641,7 @@ static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
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dpa_ctl |= DP_PLL_FREQ_270MHZ;
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}
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I915_WRITE(DP_A, dpa_ctl);
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POSTING_READ(DP_A);
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udelay(500);
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}
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@ -1708,6 +1709,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_PATTERN_2;
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I915_WRITE(fdi_rx_reg, temp);
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POSTING_READ(fdi_rx_reg);
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udelay(150);
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tries = 0;
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@ -1788,6 +1790,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
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temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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temp |= snb_b_fdi_train_param[i];
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I915_WRITE(fdi_tx_reg, temp);
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POSTING_READ(fdi_tx_reg);
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udelay(500);
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temp = I915_READ(fdi_rx_iir_reg);
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@ -1823,6 +1826,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
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temp |= FDI_LINK_TRAIN_PATTERN_2;
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}
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I915_WRITE(fdi_rx_reg, temp);
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POSTING_READ(fdi_rx_reg);
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udelay(150);
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for (i = 0; i < 4; i++ ) {
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@ -1830,6 +1834,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
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temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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temp |= snb_b_fdi_train_param[i];
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I915_WRITE(fdi_tx_reg, temp);
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POSTING_READ(fdi_tx_reg);
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udelay(500);
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temp = I915_READ(fdi_rx_iir_reg);
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