Merge branch 'remotes/lorenzo/pci/amlogic'
- Add Amlogic AXG MIPI/PCIe PHY driver and related DT bindings (Remi
Pommarel)
- Use shared PHY driver for Amlogic AXG and G12A platforms (Remi
Pommarel)
* remotes/lorenzo/pci/amlogic:
PCI: amlogic: Use AXG PCIE
phy: amlogic: Add Amlogic AXG PCIE PHY Driver
phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver
dt-bindings: PCI: meson: Update PCIE bindings documentation
dt-bindings: Add AXG shared MIPI/PCIE analog PHY bindings
dt-bindings: Add AXG PCIE PHY bindings
This commit is contained in:
Bjorn Helgaas
commit
d620d86426
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@ -18,7 +18,6 @@ Required properties:
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- reg-names: Must be
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- "elbi" External local bus interface registers
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- "cfg" Meson specific registers
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- "phy" Meson PCIE PHY registers for AXG SoC Family
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- "config" PCIe configuration space
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- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
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- clocks: Must contain an entry for each entry in clock-names.
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@ -26,13 +25,13 @@ Required properties:
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- "pclk" PCIe GEN 100M PLL clock
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- "port" PCIe_x(A or B) RC clock gate
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- "general" PCIe Phy clock
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- "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
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- resets: phandle to the reset lines.
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- reset-names: must contain "phy" "port" and "apb"
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- "phy" Share PHY reset for AXG SoC Family
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- reset-names: must contain "port" and "apb"
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- "port" Port A or B reset
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- "apb" Share APB reset
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- phys: should contain a phandle to the shared phy for G12A SoC Family
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- phys: should contain a phandle to the PCIE phy
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- phy-names: must contain "pcie"
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- device_type:
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should be "pci". As specified in designware-pcie.txt
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@ -43,9 +42,8 @@ Example configuration:
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compatible = "amlogic,axg-pcie", "snps,dw-pcie";
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reg = <0x0 0xf9800000 0x0 0x400000
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0x0 0xff646000 0x0 0x2000
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0x0 0xff644000 0x0 0x2000
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0x0 0xf9f00000 0x0 0x100000>;
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reg-names = "elbi", "cfg", "phy", "config";
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reg-names = "elbi", "cfg", "config";
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reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
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#interrupt-cells = <1>;
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@ -58,17 +56,15 @@ Example configuration:
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ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
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clocks = <&clkc CLKID_USB
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&clkc CLKID_MIPI_ENABLE
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&clkc CLKID_PCIE_A
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&clkc CLKID_PCIE_CML_EN0>;
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clock-names = "general",
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"mipi",
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"pclk",
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"port";
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resets = <&reset RESET_PCIE_PHY>,
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<&reset RESET_PCIE_A>,
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resets = <&reset RESET_PCIE_A>,
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<&reset RESET_PCIE_APB>;
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reset-names = "phy",
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"port",
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reset-names = "port",
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"apb";
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phys = <&pcie_phy>;
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phy-names = "pcie";
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};
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@ -0,0 +1,35 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic AXG shared MIPI/PCIE analog PHY
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maintainers:
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- Remi Pommarel <repk@triplefau.lt>
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properties:
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compatible:
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const: amlogic,axg-mipi-pcie-analog-phy
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reg:
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maxItems: 1
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"#phy-cells":
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const: 1
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required:
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- compatible
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- reg
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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mpphy: phy@0 {
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compatible = "amlogic,axg-mipi-pcie-analog-phy";
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reg = <0x0 0x0 0x0 0xc>;
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#phy-cells = <1>;
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};
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@ -0,0 +1,52 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic AXG PCIE PHY
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maintainers:
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- Remi Pommarel <repk@triplefau.lt>
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properties:
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compatible:
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const: amlogic,axg-pcie-phy
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reg:
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maxItems: 1
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resets:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: analog
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- phys
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- phy-names
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- resets
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
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#include <dt-bindings/phy/phy.h>
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pcie_phy: pcie-phy@ff644000 {
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compatible = "amlogic,axg-pcie-phy";
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reg = <0x0 0xff644000 0x0 0x1c>;
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resets = <&reset RESET_PCIE_PHY>;
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phys = <&mipi_analog_phy PHY_TYPE_PCIE>;
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phy-names = "analog";
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#phy-cells = <0>;
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};
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@ -66,7 +66,6 @@
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#define PORT_CLK_RATE 100000000UL
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#define MAX_PAYLOAD_SIZE 256
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#define MAX_READ_REQ_SIZE 256
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#define MESON_PCIE_PHY_POWERUP 0x1c
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#define PCIE_RESET_DELAY 500
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#define PCIE_SHARED_RESET 1
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#define PCIE_NORMAL_RESET 0
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@ -81,26 +80,19 @@ enum pcie_data_rate {
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struct meson_pcie_mem_res {
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void __iomem *elbi_base;
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void __iomem *cfg_base;
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void __iomem *phy_base;
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};
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struct meson_pcie_clk_res {
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struct clk *clk;
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struct clk *mipi_gate;
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struct clk *port_clk;
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struct clk *general_clk;
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};
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struct meson_pcie_rc_reset {
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struct reset_control *phy;
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struct reset_control *port;
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struct reset_control *apb;
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};
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struct meson_pcie_param {
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bool has_shared_phy;
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};
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struct meson_pcie {
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struct dw_pcie pci;
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struct meson_pcie_mem_res mem_res;
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@ -108,7 +100,6 @@ struct meson_pcie {
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struct meson_pcie_rc_reset mrst;
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struct gpio_desc *reset_gpio;
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struct phy *phy;
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const struct meson_pcie_param *param;
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};
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static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
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@ -130,13 +121,6 @@ static int meson_pcie_get_resets(struct meson_pcie *mp)
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{
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struct meson_pcie_rc_reset *mrst = &mp->mrst;
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if (!mp->param->has_shared_phy) {
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mrst->phy = meson_pcie_get_reset(mp, "phy", PCIE_SHARED_RESET);
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if (IS_ERR(mrst->phy))
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return PTR_ERR(mrst->phy);
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reset_control_deassert(mrst->phy);
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}
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mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
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if (IS_ERR(mrst->port))
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return PTR_ERR(mrst->port);
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@ -162,22 +146,6 @@ static void __iomem *meson_pcie_get_mem(struct platform_device *pdev,
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return devm_ioremap_resource(dev, res);
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}
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static void __iomem *meson_pcie_get_mem_shared(struct platform_device *pdev,
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struct meson_pcie *mp,
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const char *id)
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{
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struct device *dev = mp->pci.dev;
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struct resource *res;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
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if (!res) {
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dev_err(dev, "No REG resource %s\n", id);
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return ERR_PTR(-ENXIO);
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}
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return devm_ioremap(dev, res->start, resource_size(res));
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}
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static int meson_pcie_get_mems(struct platform_device *pdev,
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struct meson_pcie *mp)
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{
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@ -189,14 +157,6 @@ static int meson_pcie_get_mems(struct platform_device *pdev,
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if (IS_ERR(mp->mem_res.cfg_base))
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return PTR_ERR(mp->mem_res.cfg_base);
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/* Meson AXG SoC has two PCI controllers use same phy register */
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if (!mp->param->has_shared_phy) {
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mp->mem_res.phy_base =
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meson_pcie_get_mem_shared(pdev, mp, "phy");
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if (IS_ERR(mp->mem_res.phy_base))
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return PTR_ERR(mp->mem_res.phy_base);
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}
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return 0;
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}
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@ -204,37 +164,33 @@ static int meson_pcie_power_on(struct meson_pcie *mp)
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{
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int ret = 0;
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if (mp->param->has_shared_phy) {
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ret = phy_init(mp->phy);
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if (ret)
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return ret;
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ret = phy_init(mp->phy);
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if (ret)
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return ret;
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ret = phy_power_on(mp->phy);
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if (ret) {
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phy_exit(mp->phy);
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return ret;
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}
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} else
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writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base);
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ret = phy_power_on(mp->phy);
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if (ret) {
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phy_exit(mp->phy);
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return ret;
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}
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return 0;
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}
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static void meson_pcie_power_off(struct meson_pcie *mp)
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{
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phy_power_off(mp->phy);
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phy_exit(mp->phy);
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}
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static int meson_pcie_reset(struct meson_pcie *mp)
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{
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struct meson_pcie_rc_reset *mrst = &mp->mrst;
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int ret = 0;
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if (mp->param->has_shared_phy) {
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ret = phy_reset(mp->phy);
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if (ret)
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return ret;
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} else {
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reset_control_assert(mrst->phy);
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udelay(PCIE_RESET_DELAY);
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reset_control_deassert(mrst->phy);
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udelay(PCIE_RESET_DELAY);
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}
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ret = phy_reset(mp->phy);
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if (ret)
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return ret;
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reset_control_assert(mrst->port);
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reset_control_assert(mrst->apb);
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@ -286,12 +242,6 @@ static int meson_pcie_probe_clocks(struct meson_pcie *mp)
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if (IS_ERR(res->port_clk))
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return PTR_ERR(res->port_clk);
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if (!mp->param->has_shared_phy) {
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res->mipi_gate = meson_pcie_probe_clock(dev, "mipi", 0);
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if (IS_ERR(res->mipi_gate))
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return PTR_ERR(res->mipi_gate);
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}
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res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
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if (IS_ERR(res->general_clk))
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return PTR_ERR(res->general_clk);
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@ -562,7 +512,6 @@ static const struct dw_pcie_ops dw_pcie_ops = {
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static int meson_pcie_probe(struct platform_device *pdev)
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{
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const struct meson_pcie_param *match_data;
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci;
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struct meson_pcie *mp;
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@ -576,17 +525,10 @@ static int meson_pcie_probe(struct platform_device *pdev)
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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match_data = of_device_get_match_data(dev);
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if (!match_data) {
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dev_err(dev, "failed to get match data\n");
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return -ENODEV;
|
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}
|
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mp->param = match_data;
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|
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if (mp->param->has_shared_phy) {
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mp->phy = devm_phy_get(dev, "pcie");
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if (IS_ERR(mp->phy))
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return PTR_ERR(mp->phy);
|
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mp->phy = devm_phy_get(dev, "pcie");
|
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if (IS_ERR(mp->phy)) {
|
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dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
|
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return PTR_ERR(mp->phy);
|
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}
|
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|
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mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
|
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|
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@ -636,30 +578,16 @@ static int meson_pcie_probe(struct platform_device *pdev)
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return 0;
|
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|
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err_phy:
|
||||
if (mp->param->has_shared_phy) {
|
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phy_power_off(mp->phy);
|
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phy_exit(mp->phy);
|
||||
}
|
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|
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meson_pcie_power_off(mp);
|
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return ret;
|
||||
}
|
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|
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static struct meson_pcie_param meson_pcie_axg_param = {
|
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.has_shared_phy = false,
|
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};
|
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|
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static struct meson_pcie_param meson_pcie_g12a_param = {
|
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.has_shared_phy = true,
|
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};
|
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|
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static const struct of_device_id meson_pcie_of_match[] = {
|
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{
|
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.compatible = "amlogic,axg-pcie",
|
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.data = &meson_pcie_axg_param,
|
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},
|
||||
{
|
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.compatible = "amlogic,g12a-pcie",
|
||||
.data = &meson_pcie_g12a_param,
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -59,3 +59,25 @@ config PHY_MESON_G12A_USB3_PCIE
|
|||
Enable this to support the Meson USB3 + PCIE Combo PHY found
|
||||
in Meson G12A SoCs.
|
||||
If unsure, say N.
|
||||
|
||||
config PHY_MESON_AXG_PCIE
|
||||
tristate "Meson AXG PCIE PHY driver"
|
||||
default ARCH_MESON
|
||||
depends on OF && (ARCH_MESON || COMPILE_TEST)
|
||||
select GENERIC_PHY
|
||||
select REGMAP_MMIO
|
||||
help
|
||||
Enable this to support the Meson MIPI + PCIE PHY found
|
||||
in Meson AXG SoCs.
|
||||
If unsure, say N.
|
||||
|
||||
config PHY_MESON_AXG_MIPI_PCIE_ANALOG
|
||||
tristate "Meson AXG MIPI + PCIE analog PHY driver"
|
||||
default ARCH_MESON
|
||||
depends on OF && (ARCH_MESON || COMPILE_TEST)
|
||||
select GENERIC_PHY
|
||||
select REGMAP_MMIO
|
||||
help
|
||||
Enable this to support the Meson MIPI + PCIE analog PHY
|
||||
found in Meson AXG SoCs.
|
||||
If unsure, say N.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
|
||||
obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
|
||||
obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o
|
||||
obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o
|
||||
obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o
|
||||
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
|
||||
obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
|
||||
obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o
|
||||
obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o
|
||||
obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o
|
||||
obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o
|
||||
obj-$(CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG) += phy-meson-axg-mipi-pcie-analog.o
|
||||
|
|
|
|||
188
drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c
Normal file
188
drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Amlogic AXG MIPI + PCIE analog PHY driver
|
||||
*
|
||||
* Copyright (C) 2019 Remi Pommarel <repk@triplefau.lt>
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
#define HHI_MIPI_CNTL0 0x00
|
||||
#define HHI_MIPI_CNTL0_COMMON_BLOCK GENMASK(31, 28)
|
||||
#define HHI_MIPI_CNTL0_ENABLE BIT(29)
|
||||
#define HHI_MIPI_CNTL0_BANDGAP BIT(26)
|
||||
#define HHI_MIPI_CNTL0_DECODE_TO_RTERM GENMASK(15, 12)
|
||||
#define HHI_MIPI_CNTL0_OUTPUT_EN BIT(3)
|
||||
|
||||
#define HHI_MIPI_CNTL1 0x01
|
||||
#define HHI_MIPI_CNTL1_CH0_CML_PDR_EN BIT(12)
|
||||
#define HHI_MIPI_CNTL1_LP_ABILITY GENMASK(5, 4)
|
||||
#define HHI_MIPI_CNTL1_LP_RESISTER BIT(3)
|
||||
#define HHI_MIPI_CNTL1_INPUT_SETTING BIT(2)
|
||||
#define HHI_MIPI_CNTL1_INPUT_SEL BIT(1)
|
||||
#define HHI_MIPI_CNTL1_PRBS7_EN BIT(0)
|
||||
|
||||
#define HHI_MIPI_CNTL2 0x02
|
||||
#define HHI_MIPI_CNTL2_CH_PU GENMASK(31, 25)
|
||||
#define HHI_MIPI_CNTL2_CH_CTL GENMASK(24, 19)
|
||||
#define HHI_MIPI_CNTL2_CH0_DIGDR_EN BIT(18)
|
||||
#define HHI_MIPI_CNTL2_CH_DIGDR_EN BIT(17)
|
||||
#define HHI_MIPI_CNTL2_LPULPS_EN BIT(16)
|
||||
#define HHI_MIPI_CNTL2_CH_EN(n) BIT(15 - (n))
|
||||
#define HHI_MIPI_CNTL2_CH0_LP_CTL GENMASK(10, 1)
|
||||
|
||||
struct phy_axg_mipi_pcie_analog_priv {
|
||||
struct phy *phy;
|
||||
unsigned int mode;
|
||||
struct regmap *regmap;
|
||||
};
|
||||
|
||||
static const struct regmap_config phy_axg_mipi_pcie_analog_regmap_conf = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = HHI_MIPI_CNTL2,
|
||||
};
|
||||
|
||||
static int phy_axg_mipi_pcie_analog_power_on(struct phy *phy)
|
||||
{
|
||||
struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy);
|
||||
|
||||
/* MIPI not supported yet */
|
||||
if (priv->mode != PHY_TYPE_PCIE)
|
||||
return -EINVAL;
|
||||
|
||||
regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
|
||||
HHI_MIPI_CNTL0_BANDGAP, HHI_MIPI_CNTL0_BANDGAP);
|
||||
|
||||
regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
|
||||
HHI_MIPI_CNTL0_ENABLE, HHI_MIPI_CNTL0_ENABLE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_axg_mipi_pcie_analog_power_off(struct phy *phy)
|
||||
{
|
||||
struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy);
|
||||
|
||||
/* MIPI not supported yet */
|
||||
if (priv->mode != PHY_TYPE_PCIE)
|
||||
return -EINVAL;
|
||||
|
||||
regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
|
||||
HHI_MIPI_CNTL0_BANDGAP, 0);
|
||||
regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
|
||||
HHI_MIPI_CNTL0_ENABLE, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_axg_mipi_pcie_analog_init(struct phy *phy)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_axg_mipi_pcie_analog_exit(struct phy *phy)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops phy_axg_mipi_pcie_analog_ops = {
|
||||
.init = phy_axg_mipi_pcie_analog_init,
|
||||
.exit = phy_axg_mipi_pcie_analog_exit,
|
||||
.power_on = phy_axg_mipi_pcie_analog_power_on,
|
||||
.power_off = phy_axg_mipi_pcie_analog_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static struct phy *phy_axg_mipi_pcie_analog_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
struct phy_axg_mipi_pcie_analog_priv *priv = dev_get_drvdata(dev);
|
||||
unsigned int mode;
|
||||
|
||||
if (args->args_count != 1) {
|
||||
dev_err(dev, "invalid number of arguments\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
mode = args->args[0];
|
||||
|
||||
/* MIPI mode is not supported yet */
|
||||
if (mode != PHY_TYPE_PCIE) {
|
||||
dev_err(dev, "invalid phy mode select argument\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
priv->mode = mode;
|
||||
return priv->phy;
|
||||
}
|
||||
|
||||
static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct phy_provider *phy;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct phy_axg_mipi_pcie_analog_priv *priv;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct regmap *map;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base)) {
|
||||
dev_err(dev, "failed to get regmap base\n");
|
||||
return PTR_ERR(base);
|
||||
}
|
||||
|
||||
map = devm_regmap_init_mmio(dev, base,
|
||||
&phy_axg_mipi_pcie_analog_regmap_conf);
|
||||
if (IS_ERR(map)) {
|
||||
dev_err(dev, "failed to get HHI regmap\n");
|
||||
return PTR_ERR(map);
|
||||
}
|
||||
priv->regmap = map;
|
||||
|
||||
priv->phy = devm_phy_create(dev, np, &phy_axg_mipi_pcie_analog_ops);
|
||||
if (IS_ERR(priv->phy)) {
|
||||
ret = PTR_ERR(priv->phy);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(dev, "failed to create PHY\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
phy_set_drvdata(priv->phy, priv);
|
||||
dev_set_drvdata(dev, priv);
|
||||
|
||||
phy = devm_of_phy_provider_register(dev,
|
||||
phy_axg_mipi_pcie_analog_xlate);
|
||||
|
||||
return PTR_ERR_OR_ZERO(phy);
|
||||
}
|
||||
|
||||
static const struct of_device_id phy_axg_mipi_pcie_analog_of_match[] = {
|
||||
{
|
||||
.compatible = "amlogic,axg-mipi-pcie-analog-phy",
|
||||
},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, phy_axg_mipi_pcie_analog_of_match);
|
||||
|
||||
static struct platform_driver phy_axg_mipi_pcie_analog_driver = {
|
||||
.probe = phy_axg_mipi_pcie_analog_probe,
|
||||
.driver = {
|
||||
.name = "phy-axg-mipi-pcie-analog",
|
||||
.of_match_table = phy_axg_mipi_pcie_analog_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(phy_axg_mipi_pcie_analog_driver);
|
||||
|
||||
MODULE_AUTHOR("Remi Pommarel <repk@triplefau.lt>");
|
||||
MODULE_DESCRIPTION("Amlogic AXG MIPI + PCIE analog PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
192
drivers/phy/amlogic/phy-meson-axg-pcie.c
Normal file
192
drivers/phy/amlogic/phy-meson-axg-pcie.c
Normal file
|
|
@ -0,0 +1,192 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Amlogic AXG PCIE PHY driver
|
||||
*
|
||||
* Copyright (C) 2020 Remi Pommarel <repk@triplefau.lt>
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
#define MESON_PCIE_REG0 0x00
|
||||
#define MESON_PCIE_COMMON_CLK BIT(4)
|
||||
#define MESON_PCIE_PORT_SEL GENMASK(3, 2)
|
||||
#define MESON_PCIE_CLK BIT(1)
|
||||
#define MESON_PCIE_POWERDOWN BIT(0)
|
||||
|
||||
#define MESON_PCIE_TWO_X1 FIELD_PREP(MESON_PCIE_PORT_SEL, 0x3)
|
||||
#define MESON_PCIE_COMMON_REF_CLK FIELD_PREP(MESON_PCIE_COMMON_CLK, 0x1)
|
||||
#define MESON_PCIE_PHY_INIT (MESON_PCIE_TWO_X1 | \
|
||||
MESON_PCIE_COMMON_REF_CLK)
|
||||
#define MESON_PCIE_RESET_DELAY 500
|
||||
|
||||
struct phy_axg_pcie_priv {
|
||||
struct phy *phy;
|
||||
struct phy *analog;
|
||||
struct regmap *regmap;
|
||||
struct reset_control *reset;
|
||||
};
|
||||
|
||||
static const struct regmap_config phy_axg_pcie_regmap_conf = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = MESON_PCIE_REG0,
|
||||
};
|
||||
|
||||
static int phy_axg_pcie_power_on(struct phy *phy)
|
||||
{
|
||||
struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
|
||||
ret = phy_power_on(priv->analog);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
regmap_update_bits(priv->regmap, MESON_PCIE_REG0,
|
||||
MESON_PCIE_POWERDOWN, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_axg_pcie_power_off(struct phy *phy)
|
||||
{
|
||||
struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
|
||||
ret = phy_power_off(priv->analog);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
regmap_update_bits(priv->regmap, MESON_PCIE_REG0,
|
||||
MESON_PCIE_POWERDOWN, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_axg_pcie_init(struct phy *phy)
|
||||
{
|
||||
struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
|
||||
ret = phy_init(priv->analog);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
regmap_write(priv->regmap, MESON_PCIE_REG0, MESON_PCIE_PHY_INIT);
|
||||
return reset_control_reset(priv->reset);
|
||||
}
|
||||
|
||||
static int phy_axg_pcie_exit(struct phy *phy)
|
||||
{
|
||||
struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
|
||||
ret = phy_exit(priv->analog);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
return reset_control_reset(priv->reset);
|
||||
}
|
||||
|
||||
static int phy_axg_pcie_reset(struct phy *phy)
|
||||
{
|
||||
struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
|
||||
int ret = 0;
|
||||
|
||||
ret = phy_reset(priv->analog);
|
||||
if (ret != 0)
|
||||
goto out;
|
||||
|
||||
ret = reset_control_assert(priv->reset);
|
||||
if (ret != 0)
|
||||
goto out;
|
||||
udelay(MESON_PCIE_RESET_DELAY);
|
||||
|
||||
ret = reset_control_deassert(priv->reset);
|
||||
if (ret != 0)
|
||||
goto out;
|
||||
udelay(MESON_PCIE_RESET_DELAY);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct phy_ops phy_axg_pcie_ops = {
|
||||
.init = phy_axg_pcie_init,
|
||||
.exit = phy_axg_pcie_exit,
|
||||
.power_on = phy_axg_pcie_power_on,
|
||||
.power_off = phy_axg_pcie_power_off,
|
||||
.reset = phy_axg_pcie_reset,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int phy_axg_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct phy_provider *pphy;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct phy_axg_pcie_priv *priv;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->phy = devm_phy_create(dev, np, &phy_axg_pcie_ops);
|
||||
if (IS_ERR(priv->phy)) {
|
||||
ret = PTR_ERR(priv->phy);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(dev, "failed to create PHY\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
priv->regmap = devm_regmap_init_mmio(dev, base,
|
||||
&phy_axg_pcie_regmap_conf);
|
||||
if (IS_ERR(priv->regmap))
|
||||
return PTR_ERR(priv->regmap);
|
||||
|
||||
priv->reset = devm_reset_control_array_get(dev, false, false);
|
||||
if (IS_ERR(priv->reset))
|
||||
return PTR_ERR(priv->reset);
|
||||
|
||||
priv->analog = devm_phy_get(dev, "analog");
|
||||
if (IS_ERR(priv->analog))
|
||||
return PTR_ERR(priv->analog);
|
||||
|
||||
phy_set_drvdata(priv->phy, priv);
|
||||
dev_set_drvdata(dev, priv);
|
||||
pphy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
|
||||
return PTR_ERR_OR_ZERO(pphy);
|
||||
}
|
||||
|
||||
static const struct of_device_id phy_axg_pcie_of_match[] = {
|
||||
{
|
||||
.compatible = "amlogic,axg-pcie-phy",
|
||||
},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, phy_axg_pcie_of_match);
|
||||
|
||||
static struct platform_driver phy_axg_pcie_driver = {
|
||||
.probe = phy_axg_pcie_probe,
|
||||
.driver = {
|
||||
.name = "phy-axg-pcie",
|
||||
.of_match_table = phy_axg_pcie_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(phy_axg_pcie_driver);
|
||||
|
||||
MODULE_AUTHOR("Remi Pommarel <repk@triplefau.lt>");
|
||||
MODULE_DESCRIPTION("Amlogic AXG PCIE PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue