net/mlx5: EQ, irq_info and rmap belong to eq_table
irq_info and rmap are EQ properties of the driver, and only needed for EQ objects, move them to the eq_table EQs database structure. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Reviewed-by: Leon Romanovsky <leonro@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
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@ -1760,7 +1760,7 @@ static void mlx5e_close_cq(struct mlx5e_cq *cq)
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static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
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{
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return cpumask_first(priv->mdev->priv.irq_info[ix + MLX5_EQ_VEC_COMP_BASE].mask);
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return cpumask_first(priv->mdev->priv.eq_table.irq_info[ix + MLX5_EQ_VEC_COMP_BASE].mask);
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}
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static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
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@ -4960,7 +4960,7 @@ int mlx5e_netdev_init(struct net_device *netdev,
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netif_carrier_off(netdev);
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#ifdef CONFIG_MLX5_EN_ARFS
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netdev->rx_cpu_rmap = mdev->rmap;
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netdev->rx_cpu_rmap = mdev->priv.eq_table.rmap;
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#endif
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return 0;
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@ -694,7 +694,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
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if (err)
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goto err_in;
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snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
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snprintf(priv->eq_table.irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
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name, pci_name(dev->pdev));
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eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
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@ -702,7 +702,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
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eq->dev = dev;
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eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
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err = request_irq(eq->irqn, handler, 0,
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priv->irq_info[vecidx].name, eq);
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priv->eq_table.irq_info[vecidx].name, eq);
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if (err)
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goto err_eq;
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@ -952,17 +952,18 @@ static int set_comp_irq_affinity_hint(struct mlx5_core_dev *mdev, int i)
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struct mlx5_priv *priv = &mdev->priv;
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int vecidx = MLX5_EQ_VEC_COMP_BASE + i;
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int irq = pci_irq_vector(mdev->pdev, vecidx);
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struct mlx5_irq_info *irq_info = &priv->eq_table.irq_info[vecidx];
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if (!zalloc_cpumask_var(&priv->irq_info[vecidx].mask, GFP_KERNEL)) {
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if (!zalloc_cpumask_var(&irq_info->mask, GFP_KERNEL)) {
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mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
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return -ENOMEM;
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}
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cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
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priv->irq_info[vecidx].mask);
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irq_info->mask);
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if (IS_ENABLED(CONFIG_SMP) &&
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irq_set_affinity_hint(irq, priv->irq_info[vecidx].mask))
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irq_set_affinity_hint(irq, irq_info->mask))
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mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
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return 0;
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@ -973,9 +974,10 @@ static void clear_comp_irq_affinity_hint(struct mlx5_core_dev *mdev, int i)
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int vecidx = MLX5_EQ_VEC_COMP_BASE + i;
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struct mlx5_priv *priv = &mdev->priv;
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int irq = pci_irq_vector(mdev->pdev, vecidx);
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struct mlx5_irq_info *irq_info = &priv->eq_table.irq_info[vecidx];
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irq_set_affinity_hint(irq, NULL);
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free_cpumask_var(priv->irq_info[vecidx].mask);
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free_cpumask_var(irq_info->mask);
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}
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static int set_comp_irq_affinity_hints(struct mlx5_core_dev *mdev)
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@ -1014,9 +1016,9 @@ static void destroy_comp_eqs(struct mlx5_core_dev *dev)
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clear_comp_irqs_affinity_hints(dev);
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#ifdef CONFIG_RFS_ACCEL
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if (dev->rmap) {
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free_irq_cpu_rmap(dev->rmap);
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dev->rmap = NULL;
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if (table->rmap) {
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free_irq_cpu_rmap(table->rmap);
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table->rmap = NULL;
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}
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#endif
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list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
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@ -1042,8 +1044,8 @@ static int create_comp_eqs(struct mlx5_core_dev *dev)
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ncomp_vec = table->num_comp_vectors;
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nent = MLX5_COMP_EQ_SIZE;
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#ifdef CONFIG_RFS_ACCEL
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dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
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if (!dev->rmap)
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table->rmap = alloc_irq_cpu_rmap(ncomp_vec);
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if (!table->rmap)
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return -ENOMEM;
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#endif
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for (i = 0; i < ncomp_vec; i++) {
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@ -1056,7 +1058,7 @@ static int create_comp_eqs(struct mlx5_core_dev *dev)
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}
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#ifdef CONFIG_RFS_ACCEL
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irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev, vecidx));
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irq_cpu_rmap_add(table->rmap, pci_irq_vector(dev->pdev, vecidx));
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#endif
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snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
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err = mlx5_create_map_eq(dev, eq, vecidx, nent, 0,
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@ -1126,9 +1128,9 @@ void mlx5_core_eq_free_irqs(struct mlx5_core_dev *dev)
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clear_comp_irqs_affinity_hints(dev);
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#ifdef CONFIG_RFS_ACCEL
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if (dev->rmap) {
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free_irq_cpu_rmap(dev->rmap);
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dev->rmap = NULL;
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if (table->rmap) {
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free_irq_cpu_rmap(table->rmap);
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table->rmap = NULL;
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}
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#endif
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list_for_each_entry(eq, &table->comp_eqs_list, list)
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@ -1160,8 +1162,8 @@ static int alloc_irq_vectors(struct mlx5_core_dev *dev)
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if (nvec <= MLX5_EQ_VEC_COMP_BASE)
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return -ENOMEM;
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priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
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if (!priv->irq_info)
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table->irq_info = kcalloc(nvec, sizeof(*table->irq_info), GFP_KERNEL);
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if (!table->irq_info)
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return -ENOMEM;
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nvec = pci_alloc_irq_vectors(dev->pdev, MLX5_EQ_VEC_COMP_BASE + 1,
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@ -1176,7 +1178,7 @@ static int alloc_irq_vectors(struct mlx5_core_dev *dev)
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return 0;
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err_free_irq_info:
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kfree(priv->irq_info);
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kfree(table->irq_info);
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return err;
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}
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@ -1185,7 +1187,7 @@ static void free_irq_vectors(struct mlx5_core_dev *dev)
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struct mlx5_priv *priv = &dev->priv;
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pci_free_irq_vectors(dev->pdev);
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kfree(priv->irq_info);
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kfree(priv->eq_table.irq_info);
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}
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int mlx5_eq_table_create(struct mlx5_core_dev *dev)
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@ -484,6 +484,10 @@ struct mlx5_eq_table {
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struct mlx5_eq pfault_eq;
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#endif
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int num_comp_vectors;
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struct mlx5_irq_info *irq_info;
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#ifdef CONFIG_RFS_ACCEL
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struct cpu_rmap *rmap;
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#endif
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};
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struct mlx5_uars_page {
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@ -640,7 +644,6 @@ struct mlx5_port_module_event_stats {
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struct mlx5_priv {
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char name[MLX5_MAX_NAME_LEN];
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struct mlx5_eq_table eq_table;
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struct mlx5_irq_info *irq_info;
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/* pages stuff */
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struct workqueue_struct *pg_wq;
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@ -851,9 +854,6 @@ struct mlx5_core_dev {
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} roce;
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#ifdef CONFIG_MLX5_FPGA
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struct mlx5_fpga_device *fpga;
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#endif
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#ifdef CONFIG_RFS_ACCEL
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struct cpu_rmap *rmap;
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#endif
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struct mlx5_clock clock;
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struct mlx5_ib_clock_info *clock_info;
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@ -1302,7 +1302,7 @@ enum {
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static inline const struct cpumask *
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mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector)
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{
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return dev->priv.irq_info[vector + MLX5_EQ_VEC_COMP_BASE].mask;
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return dev->priv.eq_table.irq_info[vector + MLX5_EQ_VEC_COMP_BASE].mask;
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}
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#endif /* MLX5_DRIVER_H */
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