s390/cpum_cf: Add new extended counters for IBM z15
Add CPU measurement counter facility event description for IBM z15. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Reviewed-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
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@ -238,6 +238,64 @@ CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
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CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
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CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
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CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
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CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
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CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
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CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083);
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CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084);
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CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085);
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CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086);
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CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087);
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CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088);
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CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089);
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CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a);
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CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b);
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CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c);
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CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d);
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CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f);
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CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
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CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
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CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
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CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
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CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
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CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
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CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
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CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
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CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
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CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
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CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
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CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
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CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
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CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
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CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
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CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
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CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
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CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
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CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
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CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
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CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
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CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
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CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
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CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
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CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
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CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
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CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
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CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
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CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
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CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
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CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1);
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CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2);
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CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8);
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CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3);
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CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4);
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CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5);
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CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7);
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CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc);
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CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108);
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CPUMF_EVENT_ATTR(cf_z15, DFLT_CCERROR, 0x00109);
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CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
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CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
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static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
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CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
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CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
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@ -516,6 +574,67 @@ static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
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NULL,
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};
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static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
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CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES),
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CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES),
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CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES),
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CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES),
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CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES),
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CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES),
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CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES),
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CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES),
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CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY),
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CPUMF_EVENT_PTR(cf_z15, TX_C_TEND),
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CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND),
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CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES),
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CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
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CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
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CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
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CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
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CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
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CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
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CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
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CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
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CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
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CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS),
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CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS),
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CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS),
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CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS),
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CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT),
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CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL),
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CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL),
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CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS),
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CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES),
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CPUMF_EVENT_PTR(cf_z15, DFLT_CC),
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CPUMF_EVENT_PTR(cf_z15, DFLT_CCERROR),
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CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
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CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
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NULL,
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};
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/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
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static struct attribute_group cpumcf_pmu_events_group = {
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@ -624,9 +743,11 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
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break;
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case 0x3906:
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case 0x3907:
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model = cpumcf_z14_pmu_event_attr;
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break;
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case 0x8561:
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case 0x8562:
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model = cpumcf_z14_pmu_event_attr;
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model = cpumcf_z15_pmu_event_attr;
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break;
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default:
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model = none;
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