drm/i915/fec: Disable FEC state.
Set the suitable bits in DP_TP_CTL to stop bit correction when DSC is disabled. v2: - rebased. - Add additional check for compression state. (Gaurav) v3: rebased. v4: - Move the code to the proper spot according to spec (Ville) - Use proper checks (manasi) v5: Remove unnecessary checks (Ville) v6: Resolve warnings. Add crtc_state as an argument to intel_disable_ddi_buf(). (Manasi) Cc: dri-devel@lists.freedesktop.org Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-17-manasi.d.navare@intel.com
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@ -3133,6 +3133,22 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
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DRM_ERROR("Timed out waiting for FEC Enable Status\n");
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}
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static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum port port = encoder->port;
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u32 val;
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if (!crtc_state->fec_enable)
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return;
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val = I915_READ(DP_TP_CTL(port));
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val &= ~DP_TP_CTL_FEC_ENABLE;
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I915_WRITE(DP_TP_CTL(port), val);
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POSTING_READ(DP_TP_CTL(port));
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}
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static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state)
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@ -3272,7 +3288,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
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}
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}
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static void intel_disable_ddi_buf(struct intel_encoder *encoder)
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static void intel_disable_ddi_buf(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum port port = encoder->port;
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@ -3291,6 +3308,9 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder)
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val |= DP_TP_CTL_LINK_TRAIN_PAT1;
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I915_WRITE(DP_TP_CTL(port), val);
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/* Disable FEC in DP Sink */
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intel_ddi_disable_fec_state(encoder, crtc_state);
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if (wait)
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intel_wait_ddi_buf_idle(dev_priv, port);
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}
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@ -3314,7 +3334,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
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intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
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}
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intel_disable_ddi_buf(encoder);
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intel_disable_ddi_buf(encoder, old_crtc_state);
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intel_edp_panel_vdd_on(intel_dp);
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intel_edp_panel_off(intel_dp);
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@ -3337,7 +3357,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
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intel_ddi_disable_pipe_clock(old_crtc_state);
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intel_disable_ddi_buf(encoder);
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intel_disable_ddi_buf(encoder, old_crtc_state);
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intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
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@ -3388,7 +3408,7 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
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val &= ~FDI_RX_ENABLE;
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I915_WRITE(FDI_RX_CTL(PIPE_A), val);
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intel_disable_ddi_buf(encoder);
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intel_disable_ddi_buf(encoder, old_crtc_state);
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intel_ddi_clk_disable(encoder);
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val = I915_READ(FDI_RX_MISC(PIPE_A));
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