Merge tag 'sdma-dts' into omap-for-v5.6/ti-sysc-dt
commit
d71b48236c
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@ -212,7 +212,7 @@
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ranges = <0x0 0x56000 0x1000>;
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sdma: dma-controller@0 {
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compatible = "ti,omap4430-sdma";
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compatible = "ti,omap4430-sdma", "ti,omap-sdma";
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reg = <0x0 0x1000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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@ -8,6 +8,7 @@
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* kind, whether express or implied.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/omap.h>
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@ -79,17 +80,38 @@
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reg = <0x480FE000 0x1000>;
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};
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sdma: dma-controller@48056000 {
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compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
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target-module@48056000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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ti,hwmods = "dma";
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reg = <0x48056000 0x1000>;
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interrupts = <12>,
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<13>,
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<14>,
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<15>;
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#dma-cells = <1>;
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dma-channels = <32>;
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dma-requests = <64>;
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reg = <0x48056000 0x4>,
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<0x4805602c 0x4>,
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<0x48056028 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_EMUFREE |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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clocks = <&core_l3_ck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x48056000 0x1000>;
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sdma: dma-controller@0 {
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compatible = "ti,omap2420-sdma", "ti,omap-sdma";
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reg = <0 0x1000>;
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interrupts = <12>,
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<13>,
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<14>,
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<15>;
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#dma-cells = <1>;
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dma-channels = <32>;
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dma-requests = <64>;
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};
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};
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i2c1: i2c@48070000 {
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@ -309,6 +309,10 @@
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};
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};
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&sdma {
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compatible = "ti,omap2430-sdma", "ti,omap-sdma";
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};
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&i2c1 {
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compatible = "ti,omap2430-i2c";
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};
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@ -482,6 +482,11 @@
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regulator-always-on;
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};
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/* First two dma channels are reserved on secure omap3 */
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&sdma {
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dma-channel-mask = <0xfffffffc>;
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};
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&twl {
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twl_audio: audio {
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compatible = "ti,twl4030-audio";
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@ -206,17 +206,42 @@
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reg = <0x48200000 0x1000>;
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};
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sdma: dma-controller@48056000 {
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compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
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reg = <0x48056000 0x1000>;
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interrupts = <12>,
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<13>,
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<14>,
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<15>;
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#dma-cells = <1>;
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dma-channels = <32>;
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dma-requests = <96>;
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target-module@48056000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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ti,hwmods = "dma";
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reg = <0x48056000 0x4>,
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<0x4805602c 0x4>,
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<0x48056028 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_EMUFREE |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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/* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */
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clocks = <&core_l3_ick>;
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clock-names = "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x48056000 0x1000>;
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sdma: dma-controller@0 {
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compatible = "ti,omap3430-sdma", "ti,omap-sdma";
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reg = <0x0 0x1000>;
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interrupts = <12>,
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<13>,
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<14>,
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<15>;
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#dma-cells = <1>;
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dma-channels = <32>;
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dma-requests = <96>;
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};
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};
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gpio1: gpio@48310000 {
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@ -223,6 +223,10 @@
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};
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};
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&sdma {
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compatible = "ti,omap3630-sdma", "ti,omap-sdma";
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};
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/* OMAP3630 needs dss_96m_fck for VENC */
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&venc {
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clocks = <&dss_tv_fck>, <&dss_96m_fck>;
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@ -160,7 +160,7 @@
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ranges = <0x0 0x56000 0x1000>;
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sdma: dma-controller@0 {
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compatible = "ti,omap4430-sdma";
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compatible = "ti,omap4430-sdma", "ti,omap-sdma";
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reg = <0x0 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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@ -237,7 +237,7 @@
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ranges = <0x0 0x56000 0x1000>;
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sdma: dma-controller@0 {
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compatible = "ti,omap4430-sdma";
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compatible = "ti,omap4430-sdma", "ti,omap-sdma";
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reg = <0x0 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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