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pinctrl: fix several typos 

use codespell to fix lots of typos over frontends.

Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
CC: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20200421142402.9524-1-zhengdejin5@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
alistair/sunxi64-5.8
Dejin Zheng 2020-04-21 22:24:02 +08:00 committed by Linus Walleij
parent f8f0aa0089
commit d71ffeb9f2
6 changed files with 8 additions and 7 deletions
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2
drivers/pinctrl/freescale/pinctrl-imx1-core.c
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@ -60,7 +60,7 @@ struct imx1_pinctrl {
/*
* IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
* control register are seperated into function, output configuration, input
* control registers are separated into function, output configuration, input
* configuration A, input configuration B, GPIO in use and data direction.
*
* Those controls that are represented by 1 bit have a direct mapping between

2
drivers/pinctrl/pinctrl-lantiq.c
View File

@ -221,7 +221,7 @@ static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux)
return i;
}
/* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */
/* don't assume .mfp is linearly mapped. find the mfp with the correct .pin */
static int match_mfp(const struct ltq_pinmux_info *info, int pin)
{
int i;

2
drivers/pinctrl/pinctrl-sx150x.c
View File

@ -988,7 +988,7 @@ static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
/*
* In order to mask the differences between 16 and 8 bit expander
* devices we set up a sligthly ficticious regmap that pretends to be
* a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh
* a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
* pair/quartet) registers and transparently reconstructs those
* registers via multiple I2C/SMBus reads
*

5
drivers/pinctrl/sh-pfc/pfc-sh7269.c
View File

@ -1963,8 +1963,9 @@ static const struct pinmux_func pinmux_func_gpios[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* "name" addr register_size Field_Width */
/* where Field_Width is 1 for single mode registers or 4 for upto 16
mode registers and modes are described in assending order [0..16] */
/* where Field_Width is 1 for single mode registers or 4 for up to 16
* mode registers and modes are described in assending order [0..15]
*/
{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,

2
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
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@ -123,7 +123,7 @@ static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
unsigned *num_pins)
{
/*
* For the tegra-xusb pad controller groups are synonomous
* For the tegra-xusb pad controller groups are synonymous
* with lanes/pins and there is always one lane/pin per group.
*/
*pins = &pinctrl->desc->pins[group].number;

2
drivers/pinctrl/zte/pinctrl-zx.c
View File

@ -94,7 +94,7 @@ static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
if (data->aon_pin) {
/*
* It's an AON pin, whose mux register offset and bit position
* can be caluculated from pin number. Each register covers 16
* can be calculated from pin number. Each register covers 16
* pins, and each pin occupies 2 bits.
*/
u16 aoffset = pindesc->number / 16 * 4;